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www.latticesemi.com 1-1 ds1015_01.6 may 2010 data sheet ds1015 ? 2010 lattice semiconductor corp. all lattice trademarks, regist ered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. features ? monitor, control, and margin multiple power supplies ? simultaneously monitors up to 12 power ? supplies ? provides up to 20 output control signals ? provides up to eight analog outputs for ? margining/trimming power supply voltages ? programmable digital and analog circuitry ? power supply margin and trim functions ? trim and margin up to eight power supplies ? dynamic voltage control through i 2 c ? four hardware selectable voltage profiles ? independent digital closed-loop trim function f or each output ? embedded pld for sequence control ? 48-macrocell cpld implements both state machines and combinatorial logic functions ? embedded programmable timers ? four independent timers ? 32s to 2 second intervals for timing sequences ? analog input monitoring ? 12 independent analog monitor inputs ? differential inputs for remote ground sense ? two programmable threshold comparators per analog input ? hardware window comparison ? 10-bit adc for i 2 c monitoring ? high-voltage fet drivers ? power supply ramp up/down control ? programmable current and voltage output ? independently configurable for fet control or d igital output ? 2-wire (i 2 c/smbus? compatible) interface ? comparator status monitor ? adc readout ? direct control of inputs and outputs ? power sequence control ? dynamic trimming/margining control ? 3.3v operation, wide supply range 2.8v to 3.96v ? in-system programmable through jtag ? industrial temperature range: -40c to +85c ? 100-pin tqfp package, lead-free option application block diagram pol#1 pol#n n igram/ m ir t cpu isppac-powr1220at8 signals 4 timers adc 6 digital inputs i 2 c interface i 2 c bus power supply margin/trim control block 12 analog inputs and voltage monitors digital monitoring other board circ u itry voltage monitoring enables 8 analog trim outputs primary supply primary supply primary supply primary supply primary supply 16 digital outputs other control/supervisory cpld 48 macrocells 83 inputs 4 mosfet drivers 3.3v 2.5v 1.8v description the lattice power manager ii isppac-powr1220at8 is a general-purpose power-supply monitor, sequence and margin controller, incorporating both in-system pro- grammable logic and in-system programmable analog functions implemented in non-volatile e 2 cmos ? tech- nology. the isppac-powr1220at8 device provides 12 independent analog input channels to monitor up to 12 power supply test points. each of these input channels offers a differential input to support remote ground sensing, and has two independently programmable comparators to support both high/low and in-bounds/ out-of-bounds (window-compare) monitor functions. six general-purpose digital inputs are also provided for mis- cellaneous control functions. the isppac-powr1220at8 provides 20 open-drain digital outputs that can be used for controlling dc-dc converters, low-drop-out regulators (ldos) and opto- couplers, as well as for supervisory and general-pur- pose logic interface functions. four of these outputs isppac-powr1220at8 in-system programmable power supply monitoring, sequencing and margining controller ?
lattice semiconductor isppac-p owr1220at8 data sheet 1-2 (hvout1-hvout4) may be configured as high-voltage mosfet drivers. in high-voltage mode these outputs can provide up to 12v for driving the gates of n-channel mo sfets so that they can be used as high-side power switches controlling the supplies with a programmab le ramp rate for both ramp up and ramp down. the isppac-powr1220at8 incorporates a 48-macrocell cpld that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. the status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the cpld array, and all digital outputs may be controlled by the cpld. four independently programmable timers can create delays and time-outs ranging from 32s to 2 seconds. the cpld is programmed using logi- builder?, an easy-to-learn language integrated into the pac-designer ? software. control sequ ences are written to monitor the status of any of the analog input channel comparators or the digital inputs. in addition to the sequence control functions, the isppac-powr1220at8 incorporates eight dacs for generating trimming voltage to control the output voltage of a dc-dc converter. the trimming voltage can be set to four hard- ware selectable preset values (voltage profiles) or can be dynamically loaded in to the dac through the i 2 c bus. additionally, each power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using the digital closed loop control mode. the operating voltage profile can either be selected using external hardware pins or through the pld outputs. the on-chip 10-bit a/d converter can both be used to monitor the v mon voltage through the i 2 c bus as well as for implementing digital closed loop mode for maintaining the output voltage of all power supplies controlled by the monitoring and trimming section of the isppac-powr1220at8 device. the i 2 c bus/smbus interface allows an external microcont roller to measure the voltages connected to the v mon inputs, read back the status of each of the v mon comparator and pld outputs, control logic signals in2 to in5, con- trol the output pins, and load the dacs for the generation of the trimming voltage of the external dc-dc converter. figure 1-1. isppac-powr1220at8 block diagram cpld 48 macrocells 83 inputs jtag logic clock oscillator timers (4) i 2 c interface adc dac dac dac dac dac margin/trim control logic l a t i g i d 6 s t u p n i s t u p n i g o l a n a 2 1 s r o t i n o m e g a t l o v d n a t e f 4 s r e v i r d n i a r d - n e p o 6 1 s t u p t u o l a t i g i d voltage output dacs (8) g n i t u o r t u p t u o l o o p vmon1+ vmon1gs vmon2+ vmon2gs vmon3+ vmon3gs vmon4+ vmon4gs vmon5+ vmon5gs vmon6+ vmon6gs vmon7+ vmon7gs vmon8+ vmon8gs vmon9+ vmon9gs vmon10+ vmon10gs vmon11+ vmon11gs vmon12+ vmon12gs vps0 vps1 in1 in2 in3 in4 in5 in6 out5/smba out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 out17 hvout1 out18 out19 out20 hvout2 hvout3 hvout4 trim1 trim2 trim3 trim4 trim5 trim6 trim7 trim8 j c c v o d t s m t k c t i d t l e s k l c d l p i d t i d t a k l c m l c s a d s b t e s e r g o r p c c v gndd (6) gnda (2) vcca vccd (3) vccinp dac dac dac
lattice semiconductor isppac-p owr1220at8 data sheet 1-3 pin descriptions number name pin type voltage range description 89 vps0 digital input vccd trim select input 0 registered by mclk 90 vps1 digital input vccd trim select input 1 registered by mclk 97 in1 2 digital input vccinp 1 pld logic input 1 registered by mclk 1in2 3 digital input vccinp 1 pld logic input 2 registered by mclk 2in3 3 digital input vccinp 1 pld logic input 3 registered by mclk 4in4 3 digital input vccinp 1 pld logic input 4 registered by mclk 6in5 3 digital input vccinp 1 pld logic input 5 registered by mclk 7in6 3 digital input vccinp 1 pld logic input 6 registered by mclk 47 vmon1 analog input -0.3v to 5.75v 4 voltage monitor 1 input 46 vmon1gs analog input -0.2v to 0.3v 5 voltage monitor 1 ground sense 50 vmon2 analog input -0.3v to 5.75v 4 voltage monitor 2 input 48 vmon2gs analog input -0.2v to 0.3v 5 voltage monitor 2 ground sense 52 vmon3 analog input -0.3v to 5.75v 4 voltage monitor 3 input 51 vmon3gs analog input -0.2v to 0.3v 5 voltage monitor 3 ground sense 54 vmon4 analog input -0.3v to 5.75v 4 voltage monitor 4 input 53 vmon4gs analog input -0.2v to 0.3v 5 voltage monitor 4 ground sense 56 vmon5 analog input -0.3v to 5.75v 4 voltage monitor 5 input 55 vmon5gs analog input -0.2v to 0.3v 5 voltage monitor 5 ground sense 58 vmon6 analog input -0.3v to 5.75v 4 voltage monitor 6 input 57 vmon6gs analog input -0.2v to 0.3v 5 voltage monitor 6 ground sense 62 vmon7 analog input -0.3v to 5.75v 4 voltage monitor 7 input 61 vmon7gs analog input -0.2v to 0.3v 5 voltage monitor 7 ground sense 64 vmon8 analog input -0.3v to 5.75v 4 voltage monitor 8 input 63 vmon8gs analog input -0.2v to 0.3v 5 voltage monitor 8 ground sense 66 vmon9 analog input -0.3v to 5.75v 4 voltage monitor 9 input 65 vmon9gs analog input -0.2v to 0.3v 5 voltage monitor 9 ground sense 68 vmon10 analog input -0.3v to 5.75v 4 voltage monitor 10 input 67 vmon10gs analog input -0.2v to 0.3v 5 voltage monitor 10 ground sense 70 vmon11 analog input -0.3v to 5.75v 4 voltage monitor 11 input 69 vmon11gs analog input -0.2v to 0.3v 5 voltage monitor 11 ground sense 72 vmon12 analog input -0.3v to 5.75v 4 voltage monitor 12 input 71 vmon12gs analog input -0.2v to 0.3v 5 voltage monitor 12 ground sense 3, 22, 36, 43, 88, 98 gndd 8 ground ground digital ground 45, 87 gnda 8 ground ground analog ground 13, 38, 94 vccd 7 power 2.8v to 3.96v core vcc, main power supply 60 vcca 7 power 2.8v to 3.96v analog power supply 5 vccinp power 2.25v to 3.6v vcc for in[1:6] inputs 33 vccj power 2.25v to 3.6v vcc for jtag logic interface pins 39 vccprog 10 power 3.0v to 3.6v vcc for e 2 programming when the device is not powered by v ccd or v cca 86 hvout1 open drain output 6 0v to 12v open-drain output 1 current source/sink 12.5a to 100a source 100a to 3000a sink high-voltage fet gate driver 1
lattice semiconductor isppac-p owr1220at8 data sheet 1-4 85 hvout2 open drain output 6 0v to 12v open-drain output 2 current source/sink 12.5a to 100a source 100a to 3000a sink high-voltage fet gate driver 2 42 hvout3 open drain output 6 0v to 12v open-drain output 3 current source/sink 12.5a to 100a source 100a to 3000a sink high-voltage fet gate driver 3 40 hvout4 open drain output 6 0v to 12v open-drain output 4 current source/sink 12.5a to 100a source 100a to 3000a sink high-voltage fet gate driver 4 8 out5_smba open drain output 6 0v to 5.5v open-drain output 5, (smbus alert active low) 9 out6 open drain output 6 0v to 5.5v open-drain output 6 10 out7 open drain output 6 0v to 5.5v open-drain output 7 11 out8 open drain output 6 0v to 5.5v open-drain output 8 12 out9 open drain output 6 0v to 5.5v open-drain output 9 14 out10 open drain output 6 0v to 5.5v open-drain output 10 15 out11 open drain output 6 0v to 5.5v open-drain output 11 16 out12 open drain output 6 0v to 5.5v open-drain output 12 17 out13 open drain output 6 0v to 5.5v open-drain output 13 18 out14 open drain output 6 0v to 5.5v open-drain output 14 19 out15 open drain output 6 0v to 5.5v open-drain output 15 20 out16 open drain output 6 0v to 5.5v open-drain output 16 21 out17 open drain output 6 0v to 5.5v open-drain output 17 23 out18 open drain output 6 0v to 5.5v open-drain output 18 24 out19 open drain output 6 0v to 5.5v open-drain output 19 25 out20 open drain output 6 0v to 5.5v open-drain output 20 84 trim1 analog output -320mv to +320mv from programmable dac offset trim dac output 1 83 trim2 analog output -320mv to +320mv from programmable dac offset trim dac output 2 82 trim3 analog output -320mv to +320mv from programmable dac offset trim dac output 3 80 trim4 analog output -320mv to +320mv from programmable dac offset trim dac output 4 79 trim5 analog output -320mv to +320mv from programmable dac offset trim dac output 5 75 trim6 analog output -320mv to +320mv from programmable dac offset trim dac output 6 74 trim7 analog output -320mv to +320mv from programmable dac offset trim dac output 7 pin descriptions (cont.) number name pin type voltage range description
lattice semiconductor isppac-p owr1220at8 data sheet 1-5 73 trim8 analog output -320mv to +320mv from programmable dac offset trim dac output 8 91 resetb 9 digital i/o 0v to 3.96v device reset (active low) 95 pldclk digital output 0v to 3.96v 250khz pld clock output (tristate), cmos output 96 mclk digital i/o 0v to 3.96v 8mhz clock i/o (tristate), cmos drive 34 tdo digital output 0v to 5.5v jtag test data out 37 tck digital input 0v to 5.5v jtag test clock input 28 tms digital input 0v to 5.5v jtag test mode select 31 tdi digital input 0v to 5.5v jtag test data in, tdisel pin = 1 30 atdi digital input 0v to 5.5v jtag test data in (alternate), tdisel pin = 0 32 tdisel digital input 0v to 5.5v select tdi/atdi input 92 scl digital input 0v to 5.5v i 2 c serial clock input 93 sda digital i/o 0v to 5.5v i 2 c serial data, bi-directional pin 44, 59 reserved reserved - do not connect 26, 27, 29, 35, 41, 49, 76, 77, 78, 81, 99, 100 nc no internal connection 1. [in1...in6] are inputs to the pld. the thresholds for these pins are referenced by the voltage on vccinp. 2. in1 pin can also be controlled through jtag interface. 3. [in2..in6] can also be controlled through i 2 c/smbus interface. 4. the vmon inputs can be biased independently from vcca. unused vmons should be tied to gndd. 5. the vmongs inputs are the ground sense line for each given vmon pin. the vmon input pins along with the vmongs ground sense pins implement a differential pair for each voltage monitor to allo w remote sense at the load. vmongs lines must be connected a nd are not to exceed -0.2v - +0.3v in reference to the gnda pin. 6. open-drain outputs require an exter nal pull-up resistor to a supply. 7. vccd and vcca pins must be c onnected together on the circuit board. 8. gnda and gndd pins must be connec ted together on the circuit board. 9. the resetb pin should only be used for cascading two or more isppac-powr1220at8 devices. 10. the vccprog pin must be left floating when vccd and vcca are powered. pin descriptions (cont.) number name pin type voltage range description
lattice semiconductor isppac-p owr1220at8 data sheet 1-6 absolute maximum ratings absolute maximum ratings are shown in the table below. stresses beyond those listed may cause permanent dam- age to the device. functional operation of the device at th ese or any other conditions beyond those indicated in the recommended operating conditions of this specification is not implied. recommended operating conditions esd performance symbol parameter conditions min. max. units v ccd core supply -0.5 4.5 v v cca analog supply -0.5 4.5 v v ccinp digital input supply (in[1:6]) -0.5 6 v v ccj jtag logic supply -0.5 6 v v ccprog 1 alternate e 2 programming supply 1 -0.5 4 v v in digital input voltage (all digital i/o pins) -0.5 6 v v mon+ v mon input voltage -0.5 6 v v mongs v mon input voltage ground sense -0.5 6 v v tri voltage applied to tri-stated pins hvout[1:4] -0.5 13.3 v out[5:20] -0.5 6 v i sinkmaxtotal maximum sink current on any output 23 ma t s storage temperature -65 150 o c t a ambient temperature -65 125 o c 1. the vccprog pin must be left floating when vccd and vcca are powered. symbol parameter condi tions min. max. units v ccd, v cca core supply voltage at pin 2.8 3.96 v v ccinp digital input supply for in[1:6] at pin 2.25 5.5 v v ccj jtag logic supply voltage at pin 2.25 3.6 v v ccprog alternate e 2 programming supply at pin v ccd and v cca powered no connect must be left floating v ccd and v cca not powered 3.0 3.6 v v in input voltage at digital input pins -0.3 5.5 v v mon input voltage at v mon pins -0.3 5.9 v v mongs input voltage at v mongs pins -0.2 0.3 v v out open-drain output voltage out[5:20] pins -0.3 5.5 v hvout[1:4] pins in open-drain mode -0.3 13.0 v t aprog ambient temperature during programming -40 85 o c t a ambient temperature power applied -40 85 o c pin group esd stress min. units all pins hbm 2000 v cdm 1000 v
lattice semiconductor isppac-p owr1220at8 data sheet 1-7 analog specifications voltag e monitors high voltage fet drivers symbol parameter conditions min. typ. max. units i cc 1 supply current 40 ma i ccinp supply current 5ma i ccj supply current 1ma i ccprog supply current during programming cycle 40 ma 1. includes currents on v ccd and v cca supplies. symbol parameter conditions min. typ. max. units r in input resistance 55 65 75 k : c in input capacitance 8 pf v mon range programmable trip-point range 0.075 5.734 v v z sense near-ground sense threshold 70 75 80 mv v mon accuracy absolute accuracy of any trip-point 1 0.2 0.7 % hyst hysteresis of any trip-point (relative to setting) 1% cmr common mode rejection 60 db 1. guaranteed by characterization across v cca range, operating temperature, process. symbol parameter conditions min. typ. max. units v pp gate driver output voltage 12v setting 1 11.5 12 12.5 v 10v setting 9.6 10 10.4 8v setting 7.7 8 8.3 6v setting 5.8 6 6.2 i outsrc gate driver source current (high state) four settings in software 12.5 a 25 50 100 i outsink gate driver sink current (low state) fast off mode 2000 3000 a controlled ramp settings 100 250 500 1. 12v setting only available on the isppac-powr1220at8-02.
lattice semiconductor isppac-p owr1220at8 data sheet 1-8 margin/trim dac output characteristics adc characteristics adc error budget across entire operating temperature range symbol parameter conditions min typ max units resolution 8(7+sign) bits fsr full scale range +/-320 mv lsb lsb step size 2.5 mv i out output source/sink current -200 200 a bpz bipolar zero output voltage (code=80h) offset 1 0.6 v offset 2 0.8 offset 3 1.0 offset 4 1.25 ts trimcell output voltage settling time 1 dac code changed from 80h to ffh or 80h to 00h 2.5 ms single dac code change 256 s c_load maximum load capacitance 50 pf t updatem update time through i 2 c port 2 mclk = 8mhz 260 s tose total open loop supply voltage error 3 full scale dac corre- sponds to 5% supply voltage variation -1% +1% v/v 1. to 1% of set value with 50pf load connected to trim pins. 2. total time required to update a single trimx output value by setting the associated dac through the i 2 c port. 3. this is the total resultant error in the trimmed power suppl y output voltage referred to any dac code due to the dac?s inl, d nl, gain, out- put impedance, offset error and bipolar offset error across the industrial temperature range and the isppac-powr1200at8 operati ng v cca and v ccd ranges. symbol parameter conditions min. typ. max. units adc resolution 10 bits t convert conversion time time from i 2 c request 200 s v in input range full scale programmable attenuator = 1 0 2.048 v programmable attenuator = 3 0 5.9 1 v adc step size lsb programmable attenuator = 1 2 mv programmable attenuator = 3 6 mv eattenuator error due to attenuator programmable attenuator = 3 +/- 0.1 % 1. maximum voltage is limited by v monx pin (theoretical maximum is 6.144v). symbol parameter conditi ons min. typ. max. units tadc error total measurement error at any voltage 1 measurement range 600 mv - 2.048v, vmonxgs > -100mv, attenuator =1 -8 +/-4 8 mv measurement range 600 mv - 2.048v, vmonxgs > -200mv, attenuator =1 +/-6 mv measurement range 0 - 2.048v, vmonxgs > -200mv, attenuator =1 +/-10 mv 1. total error, guaranteed by characterization, includes inl, dnl, gain, offset, and psr specs of the adc.
lattice semiconductor isppac-p owr1220at8 data sheet 1-9 power-on reset figure 1-2. isppac-powr1220ate power-on reset symbol parameter conditions min. typ. max. units t rst delay from v th to start-up state 100 s t start delay from resetb high to pldclk rising edge 510s t good power-on reset to valid vmon comparator output and agood is true 2.5 ms t bro minimum duration brown out required to trig- ger resetb 15s t por delay from brown out to reset state. 13 s v tl threshold below which resetb is low 1 2.3 v v th threshold above which resetb is high 1 2.7 v v t threshold above which resetb is valid 1 0.8 v c l capacitive load on reset b for master/slave operation 200 pf 1. corresponds to vcca and vccd supply voltages. vcc v t v tl v th resetb agood (internal) t good mclk pldclk t bro t start analog calibration reset state t rst start up state t por
lattice semiconductor isppac-p owr1220at8 data sheet 1-10 ac/transient characteristics over recommended operating conditions symbol parameter conditions min. typ. max. units voltage monitors t pd16 propagation delay input to output glitch filter off 16 s t pd64 propagation delay input to output glitch filter on 64 s oscillators f clk internal master clock frequency (mclk) 7.6 8 8.4 mhz f clkext externally applied master clock (mclk) 7.2 8.8 mhz f pldclk pldclk output frequency f clk = 8mhz 250 khz timers timeout range range of programmable timers (128 steps) f clk = 8mhz 0.032 1966 ms resolution spacing between available adjacent timer intervals 13 % accuracy timer accuracy f clk = 8mhz -6.67 -12.5 %
lattice semiconductor isppac-p owr1220at8 data sheet 1-11 digital specifications over recommended operating conditions symbol parameter conditi ons min. typ. max. units i il ,i ih input leakage, no pull-up/pull-down +/-10 a i oh-hvout output leakage current hvout[1:4] in open drain mode and pulled up to 12v 35 60 a i pu input pull-up current (tms, tdi, tdisel, atdi, mclk) 70 a v il voltage input, logic low 1 vps[0:1], tdi, tms, atdi, tdisel, 3.3v supply 0.8 v vps[0:1], tdi, tms, atdi, tdisel, 2.5v supply 0.7 scl, sda 30% v ccd in[1:6] 30% v ccinp v ih voltage input, logic high 1 vps[0:1], tdi, tms, atdi, tdisel, 3.3v supply 2.0 v vps[0:1], tdi, tms, atdi, tdisel, 2.5v supply 1.7 scl, sda 70% v ccd v ccd in[1:6] 70% v ccinp v ccinp v ol hvout[1:4] (open drain mode), i sink = 10ma 0.8 v out[5:20] i sink = 20ma 0.8 tdo, mclk, pldclk, sda i sink = 4ma 0.4 v oh tdo, mclk, pldclk i src = 4ma v ccd - 0.4 v i sinktotal all digital outputs 130 ma 1. vps[0:1], scl, sda referenced to v ccd ; in[1:6] referenced to v ccinp ; tdo, tdi, tms, atdi, tdisel referenced to v ccj .
lattice semiconductor isppac-p owr1220at8 data sheet 1-12 i 2 c port characteristics symbol definition 100khz 400khz units min. max. min. max. f i 2 c i 2 c clock/data rate 100 1 400 1 khz t su;sta after start 4.7 0.6 us t hd;sta after start 4 0.6 us t su;dat data setup 250 100 ns t su;sto stop setup 4 0.6 us t hd;dat data hold; scl= vih_min = 2.1v 0.3 3.45 0.3 0.9 us t low clock low period 4.7 1.3 us t high clock high period 4 0.6 us t f fall time; 2.25v to 0.65v 300 300 ns t r rise time; 0.65v to 2.25v 1000 300 ns t timeout detect clock low timeout 25 35 25 35 ms t por device must be operational after power-on reset 500 500 ms t buf bus free time between stop and start condition 4.7 1.3 us 1. if f i 2 c is less than 50khz, then the adc done status bit is not guaranteed to be set afte r a valid conversion request is completed. in this case, waiting for the t convert minimum time after a convert request is made is t he only way to guarantee a valid conversion is ready for readout. when f i2c is greater than 50khz, adc conversion complete is ensured by waiting for the done status bit.
lattice semiconductor isppac-p owr1220at8 data sheet 1-13 timing for jtag operations figure 1-3. erase (user erase or erase all) timing diagram figure 1-4. programming timing diagram symbol parameter conditions min. typ. max. units t ispen program enable delay time 10 ? ? s t ispdis program disable delay time 30 ? ? s t hvdis high voltage discharge time, program 30 ? ? s t hvdis high voltage discharge time, erase 200 ? ? s t cen falling edge of tck to tdo active ? ? 15 ns t cdis falling edge of tck to tdo disable ? ? 15 ns t su1 setup time 5 ? ? ns t h hold time 10 ? ? ns t ckh tck clock pulse width, high 20 ? ? ns t ckl tck clock pulse width, low 20 ? ? ns f max maximum tck clock frequency ? ? 25 mhz t co falling edge of tck to valid output ? ? 15 ns t pwv verify pulse width 30 ? ? s t pwp programming pulse width 20 ? ? ms vih vil vih vil update-ir run-test/idle (erase) select-dr scan clock to shift-ir state and shift in the discharge instruction, then clock to the run-test/idle state run-test/idle (discharge) specified by the data sheet tms tck state t h t h t h t h t h t h t su1 t su1 t su1 t su1 t su1 t su1 t su2 t ckh t ckh t ckh t ckh t ckh t gkl t gkl tms tck state vih vil vih vi l update-ir run-test/idle (program) select-dr scan clock to shift-ir state and shift in the next instruction, which will stop the discharge process update-ir t su1 t su1 t su1 t su1 t su1 t h t h t h t h t h t ckl t pwp t ckh t ckh t ckh t ckh t ckl
lattice semiconductor isppac-p owr1220at8 data sheet 1-14 figure 1-5. verify timing diagram figure 1-6. discharge timing diagram theory of operation analog monitor inputs the isppac-powr1220at8 provides 12 independently progra mmable voltage monitor input circuits as shown in figure 1-7. two individually programmable trip-point co mparators are connected to an analog monitoring input. each comparator reference has 368 programmable trip points over the range of 0.664v to 5.734v. additionally, a 75mv ?zero-detect? threshold is selectab le which allows the voltage monitors to determine if a monitored signal has dropped to ground level. this feature is especially useful for determining if a power supply?s output has decayed to a substantially inactive condition after it has been switched off. tms tck state vih vil vih vil update-ir run-test/idle (program) select-dr scan clock to shift-ir state and shift in the next instruction update-ir t h t h t h t h t h t ckh t ckh t ckh t ckl t pwv t ckh t ckl t su1 t su1 t su1 t su1 t su1 tms tck state vih vil vih vil update-ir run-test/idle (erase or program) select-dr scan clock to shift-ir state and shift in the verify instruction, then clock to the run-test/idle state run-test/idle (verify) specified by the data sheet actual t h t h t h t h t h t h t su1 t ckh t hvdis (actual) t ckh t ckh t ckh t ckl t pwp t pwv t ckh t ckl t pwv t su1 t su1 t su1 t su1 t su1
lattice semiconductor isppac-p owr1220at8 data sheet 1-15 figure 1-7. isppac-powr1220at8 voltage monitors figure 1-7 shows the functional block diagram of one of the 12 voltage monitor inputs - ?x? (where x = 1...12). each voltage monitor can be divided into three sections: analog input, window control, and filtering. the first section provides a differential input buffer to monitor the powe r supply voltage through vmonx+ (to sense the positive ter- minal of the supply) and vmonxgs (to sense the power supply ground). differential voltage sensing minimizes inaccuracies in voltage measurement with adc and monito r thresholds due to the potential difference between the isppac-powr1220at8 device ground and the ground pot ential at the sensed node on the circuit board. the voltage output of the differential input buffer is monitored by two individually programmable trip-point compara- tors, shown as compa and compb. table 1-1 shows all 368 trip points spanning the range 0.664v to 5.734v to which a comparator?s threshold can be set. each comparator outputs a high signal to the pld array if the voltage at its positive terminal is greater than its pro- grammed trip point setting, otherwise it outputs a low signal. a hysteresis of approximately 1% of the setpoint is provided by the comparators to reduce false triggering as a result of input noise. the hysteresis provided by the voltage monitor is a function of the input divider setting. table 1-3 lists the typical hysteresis versus voltage monitor trip-point. agood logic signal all the vmon comparators auto-calibrate immediately after a power-on reset event. during this time, the digital glitch filters are also initialized. th is process completion is signalled by an internally generated logic signal: agood. all logic using the vmon comparator logic sign als must wait for the agood signal to become active. programmable over-voltage and under-voltage thresholds figure 1-8 (a) shows the power supply ramp-up and ramp-down voltage waveforms. because of hysteresis, the comparator outputs change state at different thresholds depending on the direction of excursion of the monitored power supply. glitch filter mux vmonx trip point a + ? + ? comp a comp b comp a/window select vmonxb logic signal vmonxgs trip point b analog input window control filtering isppac-powr1220at8 differential input buffer x to adc vmonxa logic signal pld array vmonx status i 2 c interface unit glitch filter
lattice semiconductor isppac-p owr1220at8 data sheet 1-16 figure 1-8. (a) power supply voltage ramp-up and ramp-down waveform and the resulting comparator output, (b) corresponding to upper and lower trip points during power supply ramp-up the comparator output changes from logic 0 to 1 when the power supply voltage crosses the upper trip point (utp). during ramp down the comparator output changes from logic state 1 to 0 when the power supply voltage crosses the lower trip point (ltp ). to monitor for over voltage fault conditions, the utp should be used. to monitor under-voltage fault conditions, the ltp should be used. tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft- ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition. utp ltp monitored power supply votlage comparator logic output (a) (b)
lattice semiconductor isppac-p owr1220at8 data sheet 1-17 table 1-1. trip point table used for over-voltage detection fine range setting coarse range setting 123456789101112 1 0.790 0.941 1.120 1.333 1.580 1.885 2.244 2.665 3.156 3.758 4.818 5.734 2 0.786 0.936 1.114 1.326 1.571 1.874 2.232 2.650 3.139 3.738 4.792 5.703 3 0.782 0.930 1.108 1.319 1.563 1.864 2.220 2.636 3.123 3.718 4.766 5.674 4 0.778 0.926 1.102 1.312 1.554 1.854 2.209 2.622 3.106 3.698 4.741 5.643 5 0.773 0.921 1.096 1.305 1.546 1.844 2.197 2.607 3.089 3.678 4.715 5.612 6 0.769 0.916 1.090 1.298 1.537 1.834 2.185 2.593 3.072 3.657 4.689 5.581 7 0.765 0.911 1.084 1.290 1.529 1.825 2.173 2.579 3.056 3.637 4.663 5.550 8 0.761 0.906 1.078 1.283 1.520 1.815 2.161 2.565 3.039 3.618 4.638 5.520 9 0.756 0.901 1.072 1.276 1.512 1.805 2.149 2.550 3.022 3.598 4.612 5.489 10 0.752 0.896 1.066 1.269 1.503 1.795 2.137 2.536 3.005 3.578 4.586 5.459 11 0.748 0.891 1.060 1.262 1.495 1.785 2.125 2.522 2.988 3.558 4.561 5.428 12 0.744 0.886 1.054 1.255 1.486 1.774 2.113 2.507 2.971 3.537 4.535 5.397 13 0.739 0.881 1.048 1.248 1.478 1.764 2.101 2.493 2.954 3.517 4.509 5.366 14 0.735 0.876 1.042 1.240 1.470 1.754 2.089 2.479 2.937 3.497 4.483 5.336 15 0.731 0.871 1.036 1.233 1.461 1.744 2.077 2.465 2.920 3.477 4.457 5.305 16 0.727 0.866 1.030 1.226 1.453 1.734 2.064 2.450 2.903 3.457 4.431 5.274 17 0.723 0.861 1.024 1.219 1.444 1.724 2.052 2.436 2.886 3.437 4.406 5.244 18 0.718 0.856 1.018 1.212 1.436 1.714 2.040 2.422 2.869 3.416 4.380 5.213 19 0.714 0.851 1.012 1.205 1.427 1.704 2.028 2.407 2.852 3.396 4.355 5.183 20 0.710 0.846 1.006 1.198 1.419 1.694 2.016 2.393 2.836 3.376 4.329 5.152 21 0.706 0.841 1.000 1.190 1.410 1.684 2.004 2.379 2.819 3.356 4.303 5.121 22 0.701 0.836 0.994 1.183 1.402 1.673 1.992 2.365 2.802 3.336 4.277 5.090 23 0.697 0.831 0.988 1.176 1.393 1.663 1.980 2.350 2.785 3.316 4.251 5.059 24 0.693 0.826 0.982 1.169 1.385 1.653 1.968 2.337 2.768 3.296 4.225 5.030 25 0.689 0.821 0.976 1.162 1.376 1.643 1.956 2.323 2.752 3.276 4.199 4.999 26 0.684 0.816 0.970 1.155 1.369 1.633 1.944 2.309 2.735 3.256 4.174 4.968 27 0.680 0.810 0.964 1.148 1.361 1.623 1.932 2.294 2.718 3.236 4.149 4.937 28 0.676 0.805 0.958 1.140 1.352 1.613 1.920 2.280 2.701 3.216 4.123 4.906 29 0.672 0.800 0.952 1.133 1.344 1.603 1.908 2.266 2.684 3.196 4.097 4.876 30 0.668 0.795 0.946 1.126 ? 1.593 1.896 2.251 ? 3.176 4.071 4.845 low-v sense 75mv
lattice semiconductor isppac-p owr1220at8 data sheet 1-18 table 1-2. trip point table used for under-voltage detection fine range setting coarse range setting 123456789101112 1 0.786 0.936 1.114 1.326 1.571 1.874 2.232 2.650 3.139 3.738 4.792 5.703 2 0.782 0.930 1.108 1.319 1.563 1.864 2.220 2.636 3.123 3.718 4.766 5.674 3 0.778 0.926 1.102 1.312 1.554 1.854 2.209 2.622 3.106 3.698 4.741 5.643 4 0.773 0.921 1.096 1.305 1.546 1.844 2.197 2.607 3.089 3.678 4.715 5.612 5 0.769 0.916 1.090 1.298 1.537 1.834 2.185 2.593 3.072 3.657 4.689 5.581 6 0.765 0.911 1.084 1.290 1.529 1.825 2.173 2.579 3.056 3.637 4.663 5.550 7 0.761 0.906 1.078 1.283 1.520 1.815 2.161 2.565 3.039 3.618 4.638 5.520 8 0.756 0.901 1.072 1.276 1.512 1.805 2.149 2.550 3.022 3.598 4.612 5.489 9 0.752 0.896 1.066 1.269 1.503 1.795 2.137 2.536 3.005 3.578 4.586 5.459 10 0.748 0.891 1.060 1.262 1.495 1.785 2.125 2.522 2.988 3.558 4.561 5.428 11 0.744 0.886 1.054 1.255 1.486 1.774 2.113 2.507 2.971 3.537 4.535 5.397 12 0.739 0.881 1.048 1.248 1.478 1.764 2.101 2.493 2.954 3.517 4.509 5.366 13 0.735 0.876 1.042 1.240 1.470 1.754 2.089 2.479 2.937 3.497 4.483 5.336 14 0.731 0.871 1.036 1.233 1.461 1.744 2.077 2.465 2.920 3.477 4.457 5.305 15 0.727 0.866 1.030 1.226 1.453 1.734 2.064 2.450 2.903 3.457 4.431 5.274 16 0.723 0.861 1.024 1.219 1.444 1.724 2.052 2.436 2.886 3.437 4.406 5.244 17 0.718 0.856 1.018 1.212 1.436 1.714 2.040 2.422 2.869 3.416 4.380 5.213 18 0.714 0.851 1.012 1.205 1.427 1.704 2.028 2.407 2.852 3.396 4.355 5.183 19 0.710 0.846 1.006 1.198 1.419 1.694 2.016 2.393 2.836 3.376 4.329 5.152 20 0.706 0.841 1.000 1.190 1.410 1.684 2.004 2.379 2.819 3.356 4.303 5.121 21 0.701 0.836 0.994 1.183 1.402 1.673 1.992 2.365 2.802 3.336 4.277 5.090 22 0.697 0.831 0.988 1.176 1.393 1.663 1.980 2.350 2.785 3.316 4.251 5.059 23 0.693 0.826 0.982 1.169 1.385 1.653 1.968 2.337 2.768 3.296 4.225 5.030 24 0.689 0.821 0.976 1.162 1.376 1.643 1.956 2.323 2.752 3.276 4.199 4.999 25 0.684 0.816 0.970 1.155 1.369 1.633 1.944 2.309 2.735 3.256 4.174 4.968 26 0.680 0.810 0.964 1.148 1.361 1.623 1.932 2.294 2.718 3.236 4.149 4.937 27 0.676 0.805 0.958 1.140 1.352 1.613 1.920 2.280 2.701 3.216 4.123 4.906 28 0.672 0.800 0.952 1.133 1.344 1.603 1.908 2.266 2.684 3.196 4.097 4.876 29 0.668 0.795 0.946 1.126 1.335 1.593 1.896 2.251 2.667 3.176 4.071 4.845 30 0.664 0.790 0.940 1.119 ? 1.583 1.884 2.236 ? 3.156 4.045 4.815 low-v sense 75mv
lattice semiconductor isppac-p owr1220at8 data sheet 1-19 table 1-3. comparator hysteresis vs. trip-point the window control section of the voltage monitor circuit is an and gate (with inputs: an inverted compa ?anded? with compb signal) and a multiplexer th at supports the ability to develop a ?window? function without using any of the pld?s resources. through the use of the multiplexer, voltage monitor?s ?a? output may be set to report either the status of the ?a? comparator, or the window function of both comparator outputs. the voltage monitor?s ?a? output indicates whether the input signal is betwee n or outside the two comparator thresholds. important: this windowing function is only valid in cases where the threshold of the ?a? comparator is set to a value higher than that of the ?b? comparator. table 1-4 shows the operation of window function logic. table 1-4. voltage monitor windowing logic note that when the ?a? output of the voltage monitor circuit is set to windowing mode, the ?b? output continues to monitor the output of the ?b? comparator. this can be useful in that the ?b? output can be used to augment the win- dowing function by determining if the input is above or below the windowing range. the third section in the isppac-powr1220at8?s input voltage monitor is a digital filter. when enabled, the compar- ator output will be delayed by a filter ti me constant of 64 s, and is especially useful for reducing the possibility of false triggering from noise that may be present on the volt ages being monitored. when the filter is disabled, the comparator output will be delayed by 16 s. in both cases, enabled or disabled, the filters also provide synchroniza- tion of the input signals to the pld clock. this synchron ous sampling feature effectively eliminates the possibility of race conditions from occurring in any subsequent logic that is implemented in the isppac-powr1220at8?s inter- nal pld logic. the comparator status can be read from the i 2 c interface. for details on the i 2 c interface, please refer to the i 2 c/ smbus interface section of this data sheet. trip-point range (v) hysteresis (mv) low limit high limit 0.664 0.79 8 0.79 0.941 10 0.94 1.12 12 1.119 1.333 14 1.326 1.58 17 1.583 1.885 20 1.884 2.244 24 2.236 2.665 28 2.65 3.156 34 3.156 3.758 40 4.045 4.818 51 4.815 5.734 61 75 mv 0 (disabled) input voltage comp a comp b window (b and not a) comment v in < trip-point b < trip-point a 0 0 0 outside window, low tr i p - p o i n t b < v in < trip-point a 0 1 1 inside window trip-point b < trip-point a < v in 1 1 0 outside window, high
lattice semiconductor isppac-p owr1220at8 data sheet 1-20 vmon voltage measurement with the on -chip analog to digi tal converter (adc) the isppac-powr1220 has an on-chip analog to digital converter that can be used for measuring the voltages at the vmon inputs. the adc is also used in closed loop trimming of dc-dc converters. close loop trimming is cov- ered later in this document. figure 1-9. adc monito ring vmon1 to vmon12 figure 1-9 shows the adc circuit arrangement within the isppac-powr1220at8 device. the adc can measure all analog input voltages through the multiplexer, adc mux. the programmable attenuator between the adc mux and the adc can be configured as divided-by-3 or divided-b y-1 (no attenuation). the divided-by-3 setting is used to measure voltages from 0v to 6v range and divided-by-1 setting is used to measure the voltages from 0v to 2v range. a microcontroller can place a request for any vmon voltage measurement at any time through the i 2 c bus. upon the receipt of an i 2 c command, the adc will be connected to the i 2 c selected vmon through the adc mux. the adc output is then latched into the i 2 c readout registers. calculation the algorithm to convert the adc code to the corresponding voltage takes into consideration the attenuation bit value. in other words, if the attenuation bit is set, then the 10-bit adc result is automa tically multiplied by 3 to cal- culate the actual voltage at that v mon input. thus, the i 2 c readout register is 12 bits instead of 10 bits. the follow- ing formula can always be used to calculate the actual voltage from the adc code. voltage at the vmonx pins vmon = adc code (12 bits 1 , converted to decimal) * 2mv 1 note: adc_value_high (8 bits), adc_value_low (4 bits) read from i 2 c/smbus interface adc mux vmon1 vmon2 vmon3 vmon12 vdda vddinp adc programmable analog attenuator programmable digital multiplier internal vref- 2.048v 4 3 1 10 31 12 to closed loop trim circuit to i 2 c readout register 5 5 5 from i 2 c adc mux register from closed loop trim circuit 1 internal control signal
lattice semiconductor isppac-p owr1220at8 data sheet 1-21 pld block figure 1-10 shows the isppac-powr1220at8 pld architectu re, which is derived from the lattice's ispmach? 4000 cpld. the pld architecture allows the flexibility in designing various state machines and control functions used for power supply management. the and array has 83 inputs and generates 243 product terms. these 243 product terms are divided into three groups of 81 for each of the generic logic blocks, glb1, glb2, and glb3. each glb is made up of 16 macrocells. in total, there are 48 macrocells in the isppac-powr1220at8 device. the output signals of the isppac-powr1220at8 device are de rived from glbs as shown in figure 1-10. additionally, the glb3 generates the timer control and trimming block controls. figure 1-10. isppac-powr1220at8 pld architecture macrocell architecture the macrocell shown in figure 1-11 is the heart of the pld. the basic macrocell has five product terms that feed the or gate and the flip-flop. the flip-flop in each macrocell is independently configured. it can be programmed to function as a d-type or t-type flip-flop. combinatorial functions are realized by bypassing the flip-flop. the polarity control and xor gates provide additional flexibility for logic synthesis. the flip -flop?s clock is dr iven from the com- mon pld clock that is generated by dividing the 8 mhz master clock (mclk) by 32. the macrocell also supports asynchronous reset and preset functions, derived from either product terms, the global reset input, or the power-on reset signal. the resources within the macrocells share ro uting and contain a product term allocation array. the product term allocation array greatly expands the pld?s ab ility to implement complex logical functions by allowing logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode functions. all the digital inputs are registered by mclk and the vmon comparator outputs are registered by the pld clock to synchronize them to the pld logic. and array 83 inputs 243 pt global reset (resetb pin) output feedback 48 vmon[1-12] 24 in[1:6] timer1 timer0 timer2 timer3 timer clock irp 14 pld clock 6 4 agood glb1 generic logic block 16 macrocell 81 pt glb2 generic logic block 16 macrocell 81 pt glb3 generic logic block 16 macrocell 81 pt hvout[1..4], out[5..8] out[9..16] out[17..20] 81 81 81 pld_clt_en, pld_vps[0:1] input register input register mclk
lattice semiconductor isppac-p owr1220at8 data sheet 1-22 figure 1-11. isppac-powr1220at8 macrocell block diagram clock and timer functions figure 1-12 shows a block diagram of the isppac-powr1220at8?s internal clock and timer systems. the master clock operates at a fixed frequency of 8mhz, fr om which a fixed 250khz pld clock is derived. figure 1-12. clock and timer system the internal oscillator runs at a fixed frequency of 8 mhz. this signal is used as a source for the pld and timer clocks. it is also used for clocking the comparator outputs and clocking the digital filters in the voltage monitor cir- pt0 pt1 pt2 pt3 pt4 d/t q rp to orp clk clock polarity macrocell flip-flop provides d, t, or combinatorial output with polarity product term allocation global reset power on reset global polarity fuse for init product term block init product term internal oscillator 8mhz 32 timer 0 timer 1 timer 3 timer 2 mclk pldclk pld clock sw0 sw1 sw2 to/from pld
lattice semiconductor isppac-p owr1220at8 data sheet 1-23 cuits, adc and trim circuits. the isppac-powr1220at8 can be programmed to operate in three modes: master mode, standalone mode and slave mode. table 1-5 summarizes the operating modes of isppac-powr1220at8. table 1-5. isppac-powr1220at8 operating modes a divide-by-32 prescaler divides the internal 8mhz oscillator (o r external clock, if selected) down to 250khz for the pld clock and for the programmable timers. this pld clock may be made available on the pldclk pin by closing sw2. each of the four timers provides independent timeout intervals ranging from 32s to 1.96 seconds in 128 steps. digital outputs the isppac-powr1220at8 provides 20 digital outputs, hvout[1:4] and out[5:20]. outputs out[5:20] are per- manently configured as open drain to provide a high degree of flexibility when interfacing to logic signals, leds, opto-couplers, and power supply control inputs. the hvout[ 1:4] pins can be configured as either high voltage fet drivers or open drain outputs. each of these outputs may be controlled either from the pld or from the i 2 c bus. the determination whether a given output is under pld or i 2 c control may be made on a pin-by-pin basis (see figure 1- 13). for further deta ils on controlling the outputs through i 2 c, please see the i 2 c/smbus interface section of this data sheet. figure 1-13. digital output pin configuration high-voltage outputs in addition to being usable as digital open-drain outputs, the isppac-powr1220at8?s hvout1-hvout4 output pins can be programmed to operate as high-voltage fet drivers. figure 1-14 shows the details of the hvout gate drivers. each of these outputs may be controlled from the pld or from the i 2 c bus (see figure 1-14). for further details on controlling the outputs through i 2 c, please see the i 2 c/smbus interface section of this data sheet. timer operating mode sw0 sw1 condition comments standalone closed open when only one isppac-powr1220at8 is used. mclk pin tristated master closed closed when more than one isppac-powr1220at8 is used in a board, one of them should be configured to operate in this mode. mclk pin outputs 8mhz clock slave open closed when more than one isppac-powr1220at8s is used in a board. other t han the master, the rest of the isppac-powr1220at8s should be pro- grammed as slaves. mclk pin is input outx pin digital control from pld digital control from i 2 c register
lattice semiconductor isppac-p owr1220at8 data sheet 1-24 figure 1-14. basic function diagram for an out put in high voltage mosfet gate driver mode figure 1-14 shows the hvout circuitry when programmed as a fet driver. in this mode the output either sources current from a charge pump or sinks curr ent. the maximum voltage that the output level at the pin will rise to is also programmable between 6v and 12v. the maximum voltage levels that are required depend on the gate-to-source threshold of the fet being driven and the power supply voltage being switched. the maximum voltage level needs to be sufficient to bias the gate-to-source threshold on and also accommodate the load voltage at the fet?s source, since the source pin of the fet to provide a wide range of ramp rates is tied to the supply of the target board. when the hvout pin is sourcing current, charging a fet gate, the source current is programmable between 12.5a and 100a. when the driver is turned to the off state, the driver will sink current to ground, and this sink current is also programmable between 3000a and 100a to control the turn-off rate. programmable output voltage levels for hvout1- hvout4 there are three selectable steps for the output voltage of the fet drivers when in fet driver mode. the voltage that the pin is capable of driving to can be programmed from 6v to 12v in 2v steps. controlling power supp ly output voltage by margin/ trim block one of the key features of the isppac -powr1220at8 is its ability to make adj ustments to the power supplies that it may also be monitoring and/or sequencing. this is accomplished through the trim and margin block of the device. the trim and margin block can adjust voltages of up to eight different power supplies through trimcells as shown in figure 1-15. the dc-dc blocks in the figure represent virtually any type of dc power supply that has a trim or voltage adjustment input. this can be an off-the-shelf unit or custom circuit designed around a switching regulator ic. the interface between the isppac-powr1220at8 and the dc power supply is represented by a single resistor (r1 to r8) to simplify the diagram. each of these resistors represents a resistor network. other control signals driving the margin/trim block are: ? vps [1:0] ? control signals from devi ce pins common to all eight trimce lls, which are used to select the active voltage profile for all trimcells together. ? pld_vps[1:0] ? voltage profile selection signals generated by the pld. these signals can be used instead of the vps signals from the pins. ? adc input ? used to determine th e trimmed dc-dc converter voltage. ? pld_clt_en ? only from pld, used to enable closed loop trimming of all trimcells together. next to each dc-dc converter, four voltages are shown. these voltages correspond to the operating voltage profile of the margin/trim block. i source (12.5 to 100 a) i sink (100 to 500 a) +fast turn-off (3000a) charge pump (6 to 12v) input supply load hvoutx pin digital control from pld digital control from i 2 c register + -
lattice semiconductor isppac-p owr1220at8 data sheet 1-25 when the vps[1:0] = 00, representing voltage profile 0: (voltage profile 0 is recomm ended to be used for the nor- mal circuit operation) the output voltage of the dc-dc converter controlled by the trim 1 pin of the isppac-powr1220at8 will be 1v and that trimcell is operating in closed loop trim mode. at the same time, the dc-dc converters controlled by trim 2, trim 3 and trim 8 pins output 1.2v, 1.5v and 3.3v respectively. when the vps[1:0] = 01, representin g voltage profile 1 being active: the dc-dc output voltage controlled by trim 1, 2, 3, and 8 pins will be 1.05v, 1.26v, 1.57v, and 3.46v. these sup- ply voltages correspond to 5% above their respective normal operating voltage (also called as margin high). similarly, when vps[1:0] = 11, all dc-dc converters are margined low by 5%. figure 1-15. isppac-powr1220at8 trim and margin block there are eight trimcells in the isppac-powr1220at8 device, enabling simultaneous control of up to eight indi- vidual power supplies. each trimcell can generate up to four trimming voltages to control the output voltage of the dc-dc converter. trimcell #1 (closed loop) trimcell #2 (i 2 c update) trimcell #3 (i 2 c update) trimcell #8 (register 0) dc-dc trim-in v in 0123 1v (clt) 1.05v 0.97v 0.95v dc-dc output voltage controlled by profiles dc-dc dc-dc digital closed loop and i 2 c interface control isppac-powr1220at8 margin/trim block trim 1 trim 2 trim 3 trim 8 trim-in trim-in r1* r2* r3* r8* *indicates resistor network pld control signals pld_clt_en, pld_vps[0:1] input from adc mux read ? 10-bit adc code vps[0:1] v in v in dc-dc trim-in v in 1.2v (i 2 c) 1.26v 1.16v 1.14v 1.5v (i 2 c) 1.57v 1.45v 1.42v 3.3v (ee) 3.46v 3.20v 3.13v
lattice semiconductor isppac-p owr1220at8 data sheet 1-26 figure 1-16. trimcell driving a typical dc-dc converter figure 1-16 shows the resistor network between the trimcell #n in the isppac-powr1220at8 and the dc-dc converter. the values of these resistors depend on the type of dc-dc converter used and its operating voltage range. the method to calculate the values of the resistors r1, r2, and r3 are described in a separate application note. voltage profile control the margin / trim block of isppac-powr1220at8 consists of eight trimcells. because all eight trimcells in the margin / trim block are controlled by two common voltage profile control signals, they all operate at the same volt- age profile. these common voltage profile control signals are derived from a control multiplexer. one set of voltage profile control inputs to the co ntrol multiplexer is from a pair of device pins: vps0, vps1. the se cond set of voltage profile control inputs is from the pld: pld_vps0, pld_vps1. the selection between the two sets of voltage pro- file control signals is programmable and is stored in the e 2 cmos memory. v out v in r 3 r 1 r 2 trimcell #n dac dc-dc converter trim v out
lattice semiconductor isppac-p owr1220at8 data sheet 1-27 figure 1-17. voltage profile control trimcell architecture the trimcell block diagram is shown in figure 1-18. the 8-bit dac at the output provides the trimming voltage required to set the output voltage of a programmable supply. each trimcell can be operated in any one of the four voltage profiles. in each voltage profile the output trimming voltage can be set to a preset value. there are six 8-bit registers in each trimcell that, depending on the operational mode, set the dac value. of these, four dac values (dac register 0 to dac register 3) are stored in the e 2 cmos memory while the remaining register contents are stored in volatile registers. two multiplexers (mode mux and profile mux) control the routing of the code to the dac. the profile mux can be controlled by common trimcell voltage profile control signals. isppac-powr1220at8 margin/trim block ctrl mux vps1 vps0 pld control signals pld_vps[0:1] 2 2 int/ext select (e 2 cmos) trimcell #1 trimcell #2 trimcell #3 trimcell #4 trimcell #5 trimcell #6 trimcell #7 trimcell #8 trim 1 2 common voltage profile control signals common voltage profile control signals trim 2 trim 3 trim 4 trim 5 trim 6 trim 7 trim 8
lattice semiconductor isppac-p owr1220at8 data sheet 1-28 figure 1-18. isppac-powr1220at8 output trimcell figure 1-15 shows four power supply voltages next to each dc-dc converter. when the profile mux is set to volt- age profile 3, the dc supply controll ed by trim 1 will be at 0.95v, the dc s upply controlled by trim 2 will be at 1.14v, 1.43v for trim 3 and 3.14v for trim 8. when voltag e profile 0 is selected, trim 1 will set the supply to 1v, trim 2 and trim 3 will be set by the values that have been loaded using i 2 c at 1.2 and 1.5v, and trim 8 will be set to 3.3v. the following table summarizes the volt age profile selection and the corresponding dac output trimming voltage. the voltage profile selection is common to all eight trimcells. table 1-6. trimcell voltage profile and operating modes trimcell operation in voltage profiles 1, 2 and 3: the output trimming voltage is determined by the code stored in the dac registers 1, 2, and 3 corresponding to the selected voltage profile. trimcell operation in voltage profile 0: the voltage profile 0 has three operating modes. they are dac regis- ter 0 select mode, dac register i 2 c select mode and closed loop trim mode. the mode selection is stored in the e 2 cmos configuration memory. each of the eight trimcells can be independently set to different operating modes during voltage profile 0 mode of operation. dac register 0 select mode: the contents of dac register 0 are stored in the on-chip e 2 cmos memory. when voltage profile 0 is selected, the dac will be loaded with the va lue stored in dac register 0. pld_vps[1:0] or vps[1:0] selected voltage profile selected mode trimming voltage is controlled by 11 voltage profile 3 ? dac register 3 (e 2 cmos) 10 voltage profile 2 ? dac register 2 (e 2 cmos) 01 voltage profile 1 ? dac register 1 (e 2 cmos) 00 voltage profile 0 dac register 0 select dac register 0 (e 2 cmos) dac register i 2 c select dac register (i 2 c) digital closed loop trim closed loop trim register dac register 0 (e 2 cmos) closed loop trim register dac register 3 (e 2 cmos) voltage profile 0 mode select (e2cmos) mode mux profile mux dac 00 01 10 11 trimx 2 8 8 8 8 8 8 8 dac register (i 2 c) 8 voltage profile 3 voltage profile 2 voltage profile 1 voltage profile 0 dac register 2 (e 2 cmos) dac register 1 (e 2 cmos) from closed loop trim circuit trimcell architecture common trimcell voltage profile control
lattice semiconductor isppac-p owr1220at8 data sheet 1-29 dac register i 2 c select mode: this mode is used if the power management arrangement requires an external microcontroller to control the dc-dc converter output voltage. the microcontroller updates the contents of the dac register i 2 c on the fly to set the trimming voltage to a desired value. the dac register i 2 c is a volatile regis- ter and is reset to 80h (dac at bipolar zero) upon power-on. the external microcontroller writes the correct dac code in this dac register i 2 c before enabling the programmable power supply. digital closed loop trim mode closed loop trim mode operation can be used when tight control over the dc-dc converter output voltage at a desired value is required. the closed loop trim mechanism operates by comparing the measured output voltage of the dc-dc converter with the internally stored voltage setpoint. the difference between the setpoint and the actual dc-dc converter voltage generates an error voltage. this error voltage adjusts the dc-dc converter output volt- age toward the setpoint. this operation iterates until the setpoint and the dc-dc converter voltage are equal. figure 1-19 shows the closed loop trim operation of a trimcell. at regular intervals (as determined by the update rate control register) the isppac-powr1220at8 device initiates the closed loop power supply voltage correction cycle through the following blocks: ? non-volatile setpoint register stores the desired output voltage ? on-chip adc is used to measure the voltage of the dc-dc converter ? three-state comparator is used to compare the measured voltage from the adc with the setpoint regis - ter contents. the output of the three state comparator can be one of the following: ? +1 if the setpoint voltage is greater than the dc-dc converter voltage ? -1 if the setpoint voltage is less than the dc-dc converter voltage ? 0 if the setpoint voltage is equal to the dc-dc converter voltage ? channel polarity control determines the polarity of the error signal ? closed loop trim register is used to compute and store the dac code corresponding to the error voltage. the contents of the closed loop trim will be incremented or decremen ted depending on the channel polar - ity and the three-state comparator output. if the three-state comparator output is 0, the closed loop trim reg - ister contents are left unchanged. ?the dac in the trimcell is used to generate the analog error voltage that adjusts the attached dc-dc con - verter output voltage. figure 1-19. digital closed loop trim operation the closed loop trim cycle interval is programmable and is set by the update rate control register. the following table lists the programmable update interval that can be selected by the update rate register. adc three-state digital compare +/-1 setpoint (e 2 cmos) e 2 cmos registers (+1/0/-1) channel polarity (e 2 cmos) trimx vmonx trimin dc-dc converter vout gnd powr1220at8 dac register 3 dac register 2 closed loop trim register dac trim cell update rate control pld_clt_en dac register 1 dac register 0 dac register i 2 c profile 0 mode control (e 2 cmos) profile control (pins/ pld)
lattice semiconductor isppac-p owr1220at8 data sheet 1-30 table 1-7. output dac update rate in digital closed loop mode there is a one-to-one relationship between the selected trimcell and the corresponding vmon input for the closed loop operation. for example, if trimcell 3 is used to control the power supply in the closed loop trim mode, vmon3 must be used to monitor its output power supply voltage. the closed loop operation can only be started by activating the internally generated pld signal, called pld_clt_en, in pac-designer software. the selection of voltage profile 0, however, can be either through the pins vps0, vps1 or through the pl d signals pldvps0 and pldvps1. closed loop start-up behavior the contents of the closed loop regi ster, upon power-up, will contain a val ue 80h (bipolar-zero) value. the dac output voltage will be equal to the programmed offset voltage. usually under this condition, the power supply out- put will be close to its nominal voltage. if the power supply trimming should st art after reaching its desired output voltage, the corresponding dac code can be loaded into the closed loop trim register through i 2 c (same address as the dac register i 2 c mode) before activating the pld_clt_en signal. details of the digital to analog converter (dac) each trim cell has an 8-bit bipolar dac to set the trimming voltage (figure 1-20). the full-scale output voltage of the dac is +/- 320 mv. a code of 80h results in the dac output set at its bi-polar zero value. the voltage output from the dac is added to a programmable offset value and the resultant voltage is then applied to the trim output pin. the offset voltage is typically selected to be approximately equal to the dc-dc converter open circuit trim node voltage. this results in maximizing the dc-dc converter output voltage range. the programmed offset value can be set to 0.6v, 0.8v, 1.0v or 1.25v. this value selection is stored in e 2 cmos memory and cannot be changed dynamically. figure 1-20. offset voltage is added to dac output voltage to derive trim pad voltage update rate control value update interval 00 580 s 01 1.15 ms 10 9.22 ms 11 18.5 ms dac 7 bits + sign (-320mv to +320mv) offset (0.6v,0.8v,1.0v,1.25v) e2cmos 8 trimx pad from trim registers trimcell x
lattice semiconductor isppac-p owr1220at8 data sheet 1-31 resetb signal, reset co mmand via jtag or i 2 c activating the resetb signal (logic 0 applied to the resetb pin) or issui ng a reset instruction via jtag or i 2 c will force the outputs to the following states independent of how these outputs have been configured in the pins win- dow: ? out5-20 will go high-impedance. ? hvout pins programmed for open dr ain operation will go high-impedance. ? hvout pins programmed for fet driver mode operation will pull down. at the conclusion of the reset event, these outputs will go to the states defined by the pins window, and if a sequence has been programmed into the device, it will be re-started at the first step. the analog calibration will be re-done and consequently, the vmons, adcs, and dacs will not be operational until 2. 5 milliseconds (max.) after the conclusion of the reset event. caution: activating the resetb signal or issuing a reset command through i2c or jtag during the isppac- powr1220at8 device operation, results in the device aborting all operations and returning to the power-on reset state. the status of the power supp lies which are being enabled by the is ppac-powr1220at8 will be determined by the state of the outputs shown above. i 2 c/smbus interface i 2 c and smbus are low-speed serial interface protocols designed to enable communications among a number of devices on a circuit board. the isppac-powr1220at8 supports a 7-bit addressing of the i 2 c communications pro- tocol, as well as smbtimeout and smbalert features of the smbus, enabling it to easily integrated into many types of modern power management systems. figure 1-21 shows a typical i 2 c configuration, in which one or more isp- pac-powr1220at8s are slaved to a supervisory microcontroller. sda is used to carry data signals, while scl provides a synchronous clock signal. the smbalert lin e is only present in smbus systems. the 7-bit i 2 c address of the powr1220at8 is fully programmable through the jtag port. figure 1-21. isppac-powr1220at8 in i 2 c/smbus system in both the i 2 c and smbus protocols, the bus is controlled by a single master device at any given time. this mas- ter device generates the scl clock signal and coordinates all data transfers to and from a number of slave devices. the isppac-powr1220at8 is configured as a slave device, and cannot independently coordinate data transfers. each slave device on a given i 2 c bus is assigned a unique address. the isppac-powr1220at8 implements the 7- bit addressing portion of the standard. any 7-bit address can be assigned to the isppac-powr1220at8 device by programming through jtag. when selecting a device address, one should note that several addresses are reserved by the i 2 c and/or smbus standards, and should not be assigned to isppac-powr1220at8 devices to assure bus compatibility. table 1- 8 lists these reserved addresses. microprocessor (i 2 c master) powr1220at8 (i 2 c slave) powr1220at8 (i 2 c slave) sda sda sda scl scl scl scl/smclk (clock) sda/smdat (data) smbalert out5/ smba out5/ smba to other i 2 c devices interrupt v+
lattice semiconductor isppac-p owr1220at8 data sheet 1-32 table 1-8. i 2 c/smbus reserved slave device addresses the isppac-powr1220at8?s i 2 c/smbus interface allows data to be both written to and read from the device. a data write transaction (figure 1-22) consists of the following operations: 1. start the bus transaction 2. transmit the device address (7 bits) along with a low write bit 3. transmit the address of the register to be written to (8 bits) 4. transmit the data to be written (8 bits) 5. stop the bus transaction to start the transaction , the master device ho lds the scl line high while pulling sda low. address and data bits are then transferred on each successive scl pulse, in thr ee consecutive byte frames of 9 scl pulses. address and data are transferred on the first 8 scl clocks in each frame, while an acknowledge signal is asserted by the slave device on the 9th clock in each frame. both data and addresses are transferred in a most-significant-bit-first format. the first frame contains the 7-bit device address, with bit 8 held low to indicate a write operation. the second frame contains the register address to which data will be written, and the final frame contains the actual data to be writ- ten. note that the sda signal is only allowed to change when the scl is low, as raising sda when scl is high sig- nals the end of the transaction. figure 1-22. i 2 c write operation reading a data byte from the isppac-powr1220at8 requires two separate bus transactions (figure 1-23). the first transaction writes the register address from which a data byte is to be read. note that since no data is being written to the device, the transaction is concluded after the second byte frame. the second transaction performs the actual read. the first frame contai ns the 7-bit device address with the r/w bit held high. in the second frame the isppac-powr1220at8 asserts data out on the bus in response to the scl signal. note that the acknowledge signal in the second frame is asserted by the master device and not the isppac-powr1220at8. address r/w bit i 2 c function description smbus function 0000 000 0 general call address general call address 0000 000 1 start byte start byte 0000 001 x cbus address cbus address 0000 010 x reserved reserved 0000 011 x reserved reserved 0000 1xx x hs-mode master code hs-mode master code 0001 000 x na smbus host 0001 100 x na smbus alert response address 0101 000 x na reserved for access.bus 0110 111 x na reserved for access.bus 1100 001 x na smbus device default address 1111 0xx x 10-bit addressing 10-bit addressing 1111 1xx x reserved reserved ack ack ack start 123456789 a6 a5 a4 a3 a2 a1 a0 r7 r6 r5 r4 r3 r2 r1 r0 123456789 123456789 d7 d6 d5 d4 d3 d2 d1 d0 stop device address (7 bits) register address (8 bits) write data (8 bits) scl sda r/w note: shaded bits asserted by slave
lattice semiconductor isppac-p owr1220at8 data sheet 1-33 figure 1-23. i 2 c read operation the isppac-powr1220at8 provides 26 registers that can be accessed through its i 2 c interface. these registers provide the user with th e ability to monitor and control the device?s in puts and outputs, and transfer data to and from the device. table provides a summary of these registers. table 1-9. i 2 c control registers register address register name read /write description value after por 1, 2 0x00 vmon_status0 r vmon input status vmon[4:1] ? ? ? ? ? ? ? ? 0x01 vmon_status1 r vmon input status vmon[8:5] ? ? ? ? ? ? ? ? 0x02 vmon_status2 r vmon input status vmon[12:9] ? ? ? ? ? ? ? ? 0x03 output_status0 r output status out[8:5], hvout[4:1] ? ? ? ? ? ? ? ? 0x04 output_status1 r output status out[16:9] ? ? ? ? ? ? ? ? 0x05 output_status2 r output status out[20:17] x x x x ? ? ? ? 0x06 input_status r input status in[6:1] x x ? ? ? ? ? ? 0x07 adc_value_low r adc d[3:0] and status ? ? ? ? x x x 1 0x08 adc_value_high r adc d[11:4] ? ? ? ? ? ? ? ? 0x09 adc_mux r/w adc atten uator and mux[3:0] x x x 1 1 1 1 1 0x0a ues_byte0 r ues[7:0] ? ? ? ? ? ? ? ? 0x0b ues_byte1 r ues[15:8] ? ? ? ? ? ? ? ? 0x0c ues_byte2 r ues[23:16] ? ? ? ? ? ? ? ? 0x0d ues_byte3 r ues[31:24] ? ? ? ? ? ? ? ? 0x0e gp_output1 r/w gpout[8:1] 0 0 0 1 0 0 0 0 0x0f gp_output2 r/w gpout[16:9] 0 0 0 0 0 0 0 0 0x10 gp_output3 r/w gpout[20:17] x x x x 0 0 0 0 0x11 input_value r/w pld input register [6:2] x x 0 0 0 0 0 x 0x12 reset w resets device on write n/a 0x13 trim1_trim r/w trim dac 1 [7:0] 1 0 0 0 0 0 0 0 0x14 trim2_trim r/w trim dac 2 [7:0] 1 0 0 0 0 0 0 0 0x15 trim3_trim r/w trim dac 3 [7:0] 1 0 0 0 0 0 0 0 0x16 trim4_trim r/w trim dac 4 [7:0] 1 0 0 0 0 0 0 0 0x17 trim5_trim r/w trim dac 5 [7:0] 1 0 0 0 0 0 0 0 0x18 trim6_trim r/w trim dac 6 [7:0] 1 0 0 0 0 0 0 0 d5 d4 d3 d2 d1 d0 d6 d7 ack ack ack start 123456789 a6 a5 a4 a3 a2 a1 a0 r7 r6 r5 r4 r3 r2 r1 r0 123456789 device address (7 bits) register address (8 bits) scl sda r/w stop start 123456789 a6 a5 a4 a3 a2 a1 a0 ack 123456789 device address (7 bits) read data (8 bits) scl sda r/w stop step 1: write register address for read operation step 2: read data from that register note: shaded bits asserted by slave optional
lattice semiconductor isppac-p owr1220at8 data sheet 1-34 several registers are provided for monitoring the status of the analog inputs. the three registers vmon_status[0:2] provide the ability to read the status of the vmon out put comparators. the ability to read both the ?a? and ?b? comparators from each vmon input is provided through the vmon input registers. note that if a vmon input is configured to window comparison mode, then the corresponding vmonxa register bit will reflect the status of the window comparison. figure 1-24. vmon status registers it is also possible to directly read the value of the voltage present on any of the vmon inputs by using the isppac- powr1220at8?s adc. three registers provide the i 2 c interface to the adc (figure 1-24). figure 1-25. adc interface registers to perform an a/d conversion, one must set the input attenuator and channel selector. two input ranges may be set using the attenuator, 0 - 2.048v and 0 - 6.144v. table 1-10 shows the input attenuator settings. 0x19 trim7_trim r/w trim dac 7 [7:0] 1 0 0 0 0 0 0 0 0x1a trim8_trim r/w trim dac 8 [7:0] 1 0 0 0 0 0 0 0 1. ?x? = non-functional bit (bits read out as 1?s). 2. ??? = state depends on device configuration or input status. table 1-9. i 2 c control registers (cont.) register address register name read /write description value after por 1, 2 vmon4b vmon4a vmon3b vmon3a vmon2b vmon2a vmon1b vmon1a b7 b0 0x00 - vmon_status0 (read only) b6 b5 b4 b3 b2 b1 vmon8b vmon8a vmon7b vmon7a vmon6b vmon6a vmon5b vmon5a b7 b0 0x01 - vmon_status1 (read only) b6 b5 b4 b3 b2 b1 vmon12b vmon12a vmon11b vmon11a vmon10b vmon10a vmon9b vmon9a b7 b0 0x02 - vmon_status2 (read only) b6 b5 b4 b3 b2 b1 d3 d2 d1 d0 1 1 1 done b7 b0 0x07 - adc_value_low (read only) b6 b5 b4 b3 b2 b1 d11 d10 d9 d8 d7 d6 d5 d4 b7 b0 0x08 - adc_value_high (read only) b6 b5 b4 b3 b2 b1 x x x atten sel3 sel2 sel1 sel0 b7 b0 0x09 - adc_mux (read/write) b6 b5 b4 b3 b2 b1
lattice semiconductor isppac-p owr1220at8 data sheet 1-35 table 1-10. adc input attenuator control the input selector may be set to monitor any one of the twelve vmon inputs, the vcca input, or the vccinp input. table 1-11 shows the codes associated with each input selection. table 1-11. v mon address selection table writing a value to the adc_mux register to set the input a ttenuator and select or will automatically initiate a conver- sion. when the conversion is in process, the done bit (adc_value_low. 0) will be reset to 0. when the conver- sion is complete, this bit will be set to 1. when the conversion is complete, the result may be read out of the adc by performing two i 2 c read operations; one for adc_value_low, and one for adc_value_high. it is recom- mended that the i 2 c master load a second conversion command only after the completion of the current conversion command (waiting for the done bit to be set to 1). an al ternative would be to wait for a minimum specified time (see t convert value in the specifications) and disregard checking the done bit. note that if the i 2 c clock rate falls below 50khz (see f i 2 c note in specifications), the on ly way to insure a valid adc conversion is to wait the minimum specified time (t convert ), as the operation of the done bit at clock rates lower than that cannot be guaranteed. in other words, if the i 2 c clock rate is less than 50khz, the done bit may or may not assert even though a valid conversion result is available. to insure every adc conversion result is valid, preferred operation is to clock i 2 c at more than 50khz and verify done bit status or wait for the full t convert time period between subsequent adc convert commands. if an i 2 c request is placed before the current conversion is complete, the done bit will be set to 1 only after the second request is complete. the status of the digital input lines may also be monitored and controlled through i 2 c commands. figure 1-26 shows the i 2 c interface to the in[1:6] digital input lines. the input status may be monitored by reading the input_status register, while input values to the pld ar ray may be set by writing to the input_value register. to be able to set an input value for the pld array, the input multiplexer associated with that bit needs to be set to the i 2 c register setting in e 2 cmos memory otherwise the pld will rece ive its input from the inx pin. atten (adc_mux.4) resolu tion full-scale range 0 2mv 2.048 v 1 6mv 6.144 v select word input channel sel3 (adc_mux.3) sel2 (adc_mux.2) sel1 (adc_mux.1) sel0 (adc_mux.0) 0000vmon1 0001vmon2 0010vmon3 0011vmon4 0100vmon5 0101vmon6 0110vmon7 0111vmon8 1000vmon9 1001vmon10 1010vmon11 1011vmon12 1100vcca 1101vccinp
lattice semiconductor isppac-p owr1220at8 data sheet 1-36 figure 1-26. i 2 c digital input interface the digital outputs may also be monitored and controlled through the i 2 c interface, as shown in figure 1-27. the status of any given digital output may be read by re ading the contents of the associated output_status[2:0] register. note that in the case of the outputs, the status re flected by these registers reflects the logic signal used to drive the pin, and does not sample the actual level present on the output pin. for example, if an output is set high but is not pulled up, the output status bi t corresponding with that pin will read ?1 ?, but a high output signal will not appear on the pin. digital outputs may also be optionally controlled directly by the i 2 c bus instead of by the pld array. the outputs may be driven either from the pld orp or from the contents of the gp_output[2:0] registers with the choice user-settable in e 2 cmos memory. each output may be independently set to output from the pld or from the gp_output registers. input_status input_value 5 5 5 pld array i 2 c interface unit in[2..6] in1 userjtag bit 5 6 pld o utput / input_value register s elect (e 2 configuration) x x in6in5in4in3in2in1 b7 b0 0x06 - input_status (read only) b6 b5 b4 b3 b2 b1 xx b7 b0 0x11 - input_value (read/write) b6 b5 b4 b3 b2 b1 mux mux i6 i5 i4 i3 i2 x
lattice semiconductor isppac-p owr1220at8 data sheet 1-37 figure 1-27. i 2 c output monitor and control logic the ues word may also be read through the i 2 c interface, with the register mapping shown in figure 1-28. output_status0 output_status1 output_status2 gp_output1 gp_output2 gp_output3 20 20 hvout[1..4] out[5..20] i 2 c interface unit pld output/gp_output register select (e 2 configuration) out8 out7 out6 out5 hvou t4 hvout3 hvout2 hvout1 b7 b0 0x03 - output_status0 (read only) b6 b5 b4 b3 b2 b1 out16 out15 out14 out13 out12 out11 out10 out9 b7 b0 0x04 - output_status1 (read only) b6 b5 b4 b3 b2 b1 x x x x out20 out19 out18 out17 b7 b0 0x05 - output_status2 (read only) b6 b5 b4 b3 b2 b1 gp8 gp7 gp6 gp5_enb gp4 gp3 gp2 gp1 b7 b0 0x0e - gp_output1 (read/write) b6 b5 b4 b3 b2 b1 gp16 gp15 gp14 gp13 gp12 gp11 gp10 gp9 b7 b0 0x0f - gp_output2 (r ead/write) b6 b5 b4 b3 b2 b1 x x x x gp20 gp19 gp18 gp17 b7 b0 0x10 - gp_output3 (read/write) b6 b5 b4 b3 b2 b1 20 20 20 mux pld output routing pool
lattice semiconductor isppac-p owr1220at8 data sheet 1-38 figure 1-28. i 2 c register mapping for ues bits the i 2 c interface also provides the ability to initiate reset operations. the is ppac-powr1220at8 may be reset by issuing a write of any value to the i 2 c reset register (figure 1-29). note: the execution of the i 2 c reset command is equivalent to toggling the resetb pin of the chip. re fer to the resetb signal, reset command via jtag or i 2 c section of this data sheet for further information. figure 1-29. i 2 c reset register ues7 ues6 ues5 ues4 ues3 ues2 ues1 ues0 b7 b0 0x0a - ues_byte0 (read only) b6 b5 b4 b3 b2 b1 ues15 ues14 ues13 ues12 ues11 ues10 ues9 ues8 b7 b0 0x0b - ues_byte1 (read only) b6 b5 b4 b3 b2 b1 ues23 ues22 ues21 ues20 ues19 ues18 ues17 ues16 b7 b0 0x0c - ues_byte2 (read only) b6 b5 b4 b3 b2 b1 ues31 ues30 ues29 ues28 ues27 ues26 ues25 ues24 b7 b0 0x0d - ues_byte3 (read only) b6 b5 b4 b3 b2 b1 xxxxxxxx b7 b0 0x12 - reset (write only) b6 b5 b4 b3 b2 b1
lattice semiconductor isppac-p owr1220at8 data sheet 1-39 the isppac-powr1220at8 also provides the user with the ability to program the trim values over the i 2 c interface, by writing the appropriate binary word to the associated trim register (figure 1-30). figure 1-30. i 2 c trim registers d7 d6 d5 d4 d3 d2 d1 d0 b7 b0 0x13 - trim1_trim (read/write) b6 b5 b4 b3 b2 b1 b7 b0 0x14 - trim2_trim (read/write) b6 b5 b4 b3 b2 b1 b7 b0 0x15 - trim3_trim (read/write) b6 b5 b4 b3 b2 b1 b7 b0 0x16 - trim4_trim (read/write) b6 b5 b4 b3 b2 b1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 b7 b0 b6 b5 b4 b3 b2 b1 b7 b0 0x18 - trim6_trim (read/write) b6 b5 b4 b3 b2 b1 b7 b0 0x19 - trim7_trim (read/write) b6 b5 b4 b3 b2 b1 b7 b0 0x1a - trim8_trim (read/write) b6 b5 b4 b3 b2 b1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0x17 - trim5_trim (read/write)
lattice semiconductor isppac-p owr1220at8 data sheet 1-40 smbus smbalert function the isppac-powr1220at8 provides an smbus smbalert function so that it can request service from the bus master when it is used as part of an smbus system. this feature is supported as an alternate function of out5. when the smbalert feature is enabled, out5 is controlled by a combination of the pld orp and the gp5_enb bit (figure 1-31). note: to enable the smbalert feature, the smb_mode (eecmos bit) should be set in software. figure 1-31. isppac-powr1220at8 smbalert logic the typical flow for an smbalert transaction is as follows (figure 1-31): 1. gp5_enb bit is forced (via i 2 c write) to low 2. isppac-powr1220at8 pld logic pulls out5/smba low 3. master responds to interrupt from smba line 4. master broadcasts a read operation using the smbus alert response address (ara) 5. isppac-powr1220at8 responds to read request by transmitting its device address 6. if transmitted device address matches isppac-p owr1220at8 address, it sets gp5_enb bit high. this releases out5/smba. figure 1-32. smbalert bus transaction after out5/smba has been released, the bus master (typically a microcontroller) may opt to perform some service functions in which it may send data to or read data from the isppac-powr1220at8. as part of the service func- tions, the bus master will typically need to clear whatever condition initiated the smbal ert request, and will also need to reset gp5_enb to re-enable the smbalert function. for further information on the smbus, the user should consult the smbus standard. pld output routing pool mux mux gp5_enb smbalert logic out5/smba i 2 c interface unit pld output/gp_output register select (e 2 configuration) out5/smba mode select (e 2 configuration) ack a4 a3 a2 a1 a0 x a5 a6 start 123456789 000110 0 ack 123456789 alert response address (0001 100) slave address (7 bits) scl sda r/w stop smba note: shaded bits asserted by slave slave asserts smba slave releases smba
lattice semiconductor isppac-p owr1220at8 data sheet 1-41 designs using the smbalert feature are required to set the device?s i 2 c/smbus address to the lowest of all the addresses on that i 2 c/smbus. software-based design environment designers can configure the isppac-powr1220at8 using pac-designer, an easy to use, microsoft windows compatible program. circuit designs are entered graphica lly and then verified, all within the pac-designer environ- ment. full device programming is supported using pc parallel port i/o operations and a download cable connected to the serial programming interface pins of the isppac-powr1220at8. a library of configurations is included with basic solutions and examples of advanced circuit techniq ues are available on the lattice web site for downloading. in addition, comprehensive on-line and printed documentation is provided that covers all aspects of pac-designer operation. the pac-designer schematic window, shown in figure 1-33, provides access to all configurable isppac- powr1220at8 elements via its graphical user interface. all analog input and output pins are represented. static or non-configurable pins such as power, ground, and the serial digital interface are omitted for clarity. any element in the schematic window can be accessed via mouse operatio ns as well as menu commands. when completed, con- figurations can be saved, simulated, and downloaded to devices. figure 1-33. pac-designer isppac-powr1220at8 design entry screen in-system programming the isppac-powr1220at8 is an in-system programmable device. this is accomplished by integrating all e 2 con- figuration memory and control logic on-chip. programming is performed through a 4-wire, ieee 1149.1 compliant serial jtag interface at normal logic levels. once a device is programmed, all configuration information is stored on-chip, in non-volatile e 2 cmos memory cells. the specifics of the i eee 1149.1 serial interface and all isppac- powr1220at8 instructions are described in the jtag interface section of this data sheet.
lattice semiconductor isppac-p owr1220at8 data sheet 1-42 programming isppac-powr1220at8: alternate method some applications require that the isppac-powr1220at8 be programmed before turning the power on to the entire circuit board. to meet such application needs, the isppac-powr1220at8 provides an alternate program- ming method which enables the programming of the isppac-powr1220at8 device through the jtag chain with a separate power supply applied just to the programming section of the isppac-powr1220at8 device with the main power supply of the board turned off. three special purpose pins, vccprog, atdi and tdisel, enable programming of the un-programmed isppac- powr1220at8 under such circumstances. the vccprog pin provides power to the programming circuitry of the isppac-powr1220at8 device (when vccd and vcca are unpowered). the vccj pin must be powered to enable the jtag port. the atdi pin provides an alternate connection to the jtag header while bypassing all the un-powered devices in the jtag chain. tdisel pin enables switching between the atdi and the standard jtag signal tdi. when the internally pulled-up tdisel = 1, standard tdi pin is enabled and when the tdisel = 0, atdi is enabled. in order to use this feature the jtag signals of the isppac-powr1220at8 are connected to the header as shown in figure 1-34. note: the isppac-powr1220at8 should be the last device in the jtag chain. after programming, the vccprog pin must be left floating when the vccd and vcca pins are powered. figure 1-34. isppac-powr1220at8 alternate tdi configuration diagram alternate tdi select ion via jtag command when the tdisel pin held high and four consecutive idcode instructions are is sued, isppac-powr1220at8 responds by making its active jtag data input the atdi pin. when atdi is selected, data on its tdi pin is ignored until the jtag state machine returns to the test-logic-reset state. this method of selecting at di takes advantage of the fact that a jt ag device with an idcode register will auto- matically load its unique idcode inst ruction into the instruction register after a test-logic-reset. this jtag capability permits blind interrogation of devices so that their location in a serial chain can be identified without hav- ing to know anything about them in advance. a blind interrogation can be made using only the tms and tclk con- trol pins, which means tdi and tdo are not required for perf orming the operation. figure 1-35 illustrates the logic for selecting whether the tdi or atdi pin is the active data input to isppac-powr1220at8. tdi apply power to vcc only after confirming vccprog supply is disconnected. atdi tck tdo vccprog tms tdi tck tdo vccj tms tdi tck tms vcc tdisel vccprog vccprog for programming isppac-powr1220at8 through atdi (vcc should be off) tdo tdisel jtag signal connector other jtag device(s) isppac-powr 1220at8
lattice semiconductor isppac-p owr1220at8 data sheet 1-43 figure 1-35. isppac-powr1220at8 tdi/atdi pin selection diagram table 1-12 shows in truth table form the same conditions required to select either tdi or atdi as in the logic dia- gram found in figure 1-35. table 1-12. isppac-powr1220at8 atdi/tdi selection table please refer to the lattice application note an6068, programming the isppac-powr1220at8 in a jtag chain using atdi . the application note includes specific svf code examples and information on the use of lattice design tools to verify device operation in alternate tdi mode. vccprog power supply pin because the vccprog pin directly powers the on-chip pr ogramming circuitry, the isppac-powr1220at8 device can be programmed by applying power to the vccprog pin (without powering the entire chip though the vccd and vcca pins). in addition, to enable the on-chip jtag interface circuitry, power should be applied to the vccj pin. when the isppac-powr1220at8 is powered by the vccpro g pin, no power should be applied to the vccd and vcca pins. additionally, other than jtag i/o pins, all digital output pins are in hi-z state, hvout pins configured as mosfet driver are driven low, and all other inputs are ignored. to switch the power supply back to vccd and vcca pi ns, one should turn the vccprog supply and vccj off before turning the regular supplies on. when vccd and vcca are turned back on for normal operation, vccprog must be left floating. tdisel pin jtag state machine test-logic-reset 4 consecutive idcode commands loaded at update-ir active jtag data input pin h no yes atdi (tdi disabled) h yes no tdi (atdi disabled) l x x atdi (tdi disabled) 1 0 tdi atdi tdisel q set clr test-logic-reset 4 consecutive idcode instructions loaded at update-ir tdo tms tck jtag isppac-powr1220at8
lattice semiconductor isppac-p owr1220at8 data sheet 1-44 user electronic signature a user electronic signature (ues) feature is included in the e 2 cmos memory of the isppac-powr1220at8. this consists of 32 bits that can be configured by the user to store unique data such as id codes, revision numbers or inventory control data. the specifics of this feature are disc ussed in the ieee 1149.1 serial interface section of this data sheet. electronic security an electronic security ?fuse? (esf) bit is provided in every isppac-powr1220at8 device to prevent unauthorized readout of the e 2 cmos configuration bit patterns. once programmed, this cell prevents further access to the func- tional user bits in the device. this cell can only be erased by reprogramming the device, so the original configura- tion cannot be examined once programmed. usage of this feature is optional. the specifics of this feature are discussed in the ieee 1149.1 serial in terface section of this data sheet. production programming support once a final configuration is determined, an ascii format jedec file can be created using the pac-designer soft- ware. devices can then be ordered through the usual supply channels with the user?s specific configuration already preloaded into the devices. by virtue of its standard inte rface, compatibility is mainta ined with existing production programming equipment, giving cust omers a wide degree of freedom a nd flexibility in production planning. evaluation fixture included in the basic isppac-powr1220at8 design kit is an engineering prototype board that can be connected to the parallel port of a pc using a lattice download cabl e. it demonstrates proper layout techniques for the isp- pac-powr1220at8 and can be used in real time to check circuit operation as part of the design process. input and output connections are provided to aid in the evaluation of the isppac-powr1220at8 for a given application. (figure 1-36). figure 1-36. download from a pc ieee standard 1149. 1 interface (jtag) serial port programming interface communication wit h the isppac-powr1220at8 is facilitated via an ieee 1149.1 test access port (tap). it is used by the isppac-powr1220at8 as a serial programming interface. a brief description of the isppac-powr1220at8 jtag interface follows. for complete details of the reference specifica- tion, refer to the publication, stan dard test access port and boundary-sca n architecture, i eee std 1149.1-1990 (which now includes ieee std 1149.1a-1993). overview an ieee 1149.1 test access po rt (tap) provides the control interface for se rially accessing the di gital i/o of the isp- pac-powr1220at8. the tap controller is a state machine driven with mode and clock inputs. given in the correct sequence, instructions are shifted into an instruction register, which then determines subsequent data input, data output, and related operations. device programming is performed by addressing the configuration register, shifting ispdownload cable (6') 4 other system circuitry isppac-powr 1220at8 device pac-designer software
lattice semiconductor isppac-p owr1220at8 data sheet 1-45 data in, and then executing a program configuration instruction, after which the data is transferred to internal e 2 cmos cells. it is these non-volatile cells that store the configuration or the isppac-powr1220at8. a set of instructions are defined that access all data registers and perform other internal control operations. for compatibil- ity between compliant devices, two data registers are mandated by the ieee 1149.1 specification. others are func- tionally specified, but inclusion is stri ctly optional. finally, there are provisions for optional data registers defined by the manufacturer. the two required registers are the bypass and boundary-scan registers. figure 1-37 shows how the instruction and various data registers are organized in an isppac-powr1220at8. figure 1-37. isppac-powr1220at8 tap registers tap controller specifics the tap is controlled by the test clock (tck) and test mode select (tms) inputs. these inputs determine whether an instruction register or data register operation is performed. driven by the tck input, the tap consists of a small 16-state controller design. in a given state, the controller responds according to the level on the tms input as shown in figure 1-38. test data in (tdi) and tms are latched on the rising edge of tck, with test data out (tdo) becoming valid on the falling edg e of tck. there are six steady states within the controller: test-logic- reset, run- test/idle, shift-data-register, pause-data-register, shift-instruction-register and pause-instruction- register. but there is only one steady state for the condition when tms is set high: the test-logic-reset state. this allows a reset of the test logic within five tcks or less by keeping the tms input high. test-logic-reset is the power-on default state. address register (169 bits) e 2 cmos non-volatile memory ues register (32 bits) idcode register (32 bits) bypass register (1 bit) instruction register (8 bits) test access port (tap) logic output latch tdi tck tms tdo cfg address register (12 bits) multiplexer data register (243 bits) cfg data register (156 bits)
lattice semiconductor isppac-p owr1220at8 data sheet 1-46 figure 1-38. tap states when the correct logic sequenc e is applied to the tms and tck inputs, the tap will exit the test-logic-reset state and move to the desired state. the next state after test-logic-reset is run-test/idle. until a data or instruction shift is performed, no action will o ccur in run-test/idle (steady state = idle). after run-test/idle, either a data or instruc- tion shift is performed. the states of the data and instruction register blocks are identical to each other differing only in their entry points. when either block is entered, the first action is a capture operation. for the data regis- ters, the capture-dr state is very simple: it captures (parallel loads) data onto the selected serial data path (previ- ously chosen with the app ropriate instruction). for the instruction register, the captur e-ir state will always load the idcode instruction. it will always e nable the id register for readout if no other instru ction is loaded prior to a shift-dr operation. this, in conjunction with mandated bit codes, allows a ?blind? interrogation of any device in a compliant ieee 1149.1 serial chain. from the capture state, the tap transitions to either the shift or exit1 state. normally the shift state follows the capture state so that test data or status information can be shifted out or new data shifted in. following the shift state, the tap either returns to the run-test/idle state via the exit1 and update states or enters the pause state via exit1. the pause state is used to temporarily suspend the shifting of data through either the data or instruction register while an external operation is performed. from the pause state, shifting can resume by reentering the shift state via the exit2 state or be terminated by entering the run-test/idle state via the exit2 and update states. if the proper instruction is shifted in during a shift-ir operation, the next entry into run-test/idle initiates th e test mode (steady state = test). this is when the device is actually programmed, erased or verified. all other instructions are executed in the update state. test instructions like data registers, the ieee 1149.1 standard also mandates the inclusion of certain instructions. it outlines the function of three required and six optional instructions. any additional instructions are left exclusively for the manu- facturer to determine. the instruction word length is not mandated other than to be a minimum of two bits, with only the bypass and extest instruction code patterns being specifically called out (all ones and all zeroes respec- tively). the isppac-powr1220at8 contains the required minimum instruction set as well as one from the optional instruction set. in addition, there are several proprietary instructions that allow the device to be configured and ver- test-logic-rst run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 00 00 00 11 00 00 11 11 00 11 00 11 11 11 1 0 note: the value shown adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck.
lattice semiconductor isppac-p owr1220at8 data sheet 1-47 ified. table 1-13 lists the instructions supported by the isppac-powr1220at8 jtag test access port (tap) con- troller: table 1-13. isppac-powr1220at8 tap instruction table bypass is one of the three required instructions. it selects the bypass register to be connected between tdi and tdo and allows serial data to be transferred through the device without affecting the operation of the isppac- powr1220at8. the ieee 1149.1 standard defines the bit code of this instruction to be all ones (11111111). the required sample/preload instruction dictates the boundary-scan register be connected between tdi and tdo. the isppac-powr1220at8 has no boundary scan register, so for compatib ility it defaults to the bypass mode whenever this instruction is received. the bit code for this instruction is defi ned by lattice as shown in table 1-13. the extest (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the boundary scan register to be connected between tdi and tdo. again, since the instruction command code comments bulk_erase 0000 0011 bulk erase device bypass 1111 1111 bypass - connect tdo to tdi discharge 0001 0100 fast vpp discharge erase_done_bit 0010 0100 erases ?done? bit only extest 0000 0000 bypass - connect tdo to tdi idcode 0001 0110 read contents of manufacturer id code (32 bits) outputs_highz 0001 1000 force all outputs to high-z state, fet outputs pulled low sample/preload 00011100 sample/preload. default to bypass. program_disable 0001 1110 disable program mode program_done_bit 0010 1111 programs the done bit program_enable 0001 0101 enable program mode program_security 0000 1001 program security fuse reset 0010 0010 resets device (refer to the resetb signal, reset command via jtag or i 2 c section of this data sheet) in1_reset_jtag_bit 0001 0010 reset the jtag bit associated with in1 pin to 0 in1_set_jtag_bit 0001 0011 set the jtag bit associated with in1 pin to 1 cfg_address 0010 1011 select non-pld address register cfg_data_shift 0010 1101 non-pld data shift cfg_erase 0010 1001 erase just the non pld configuration cfg_program 0010 1110 non-pld program cfg_verify 0010 1000 vrify non-pld fusemap data pld_address_shift 0000 0001 pld_address register (169 bits) pld_data_shift 0000 0010 pld_data register (243 bits) pld_init_addr_for_prog_incr 0010 0001 initialize the address register for auto increment pld_prog_incr 0010 0111 program column register to e 2 and auto increment address register pld_program 0000 0111 program pld data register to e 2 pld_verify 0000 1010 verifies pld column data pld_verify_incr 0010 1010 load column register from e 2 and auto increment address register ues_program 0001 1010 program ues bits into e 2 ues_read 0001 0111 read contents of ues register from e 2 (32 bits)
lattice semiconductor isppac-p owr1220at8 data sheet 1-48 isppac-powr1220at8 has no boundary scan logic, the device is put in the bypass mode to ensure specification compatibility. the bit code of this instruction is defin ed by the 1149.1 standard to be all zeros (00000000). the optional idcode (identification code) instruction is incorporated in the isppac-powr1220at8 and leaves it in its functional mode when executed. it selects the device identification register to be connected between tdi and tdo. the identification register is a 32-bit shift register containing information regarding the ic manufacturer, device type and version code (figure 1-39). access to t he identification register is immediately available, via a tap data scan operation, after power-up of the device, or by issuing a test-logic-reset instruction. the bit code for this instruction is defined by lattice as shown in table 1-13. figure 1-39. isppac-powr1220at8 id code isppac-powr1220at8 s pecific instructions there are 25 unique instructions specified by lattice for the isppac-powr1220at8. these instructions are pri- marily used to interface to the various user registers and the e 2 cmos non-volatile memory. additional instructions are used to control or monitor other features of the device. a brief description of each unique instruction is provided in detail below, and the bit codes are found in table 1-13. pld_address_shift ? this instruction is used to set the addres s of the pld and/arch arrays for subsequent program or read operations. this instruction also forces the outputs into the outputs_highz. pld_data_shift ? this instruction is used to shift pld data into the register prior to programming or reading. this instruction also forces the outputs into the outputs_highz. pld_init_addr_ for_prog_incr ? this instruction prepares the pld address register for subsequent pld_prog_incr or pld_ver ify_incr instructions. pld_prog_incr ? this instruction programs the pld data register for the current address and increments the address register for the next set of data. pld_program ? this instruction programs th e selected pld and/arch array co lumn. the specific column is preselected by using pld_address_shift instruction. the progra mming occurs at the se cond rising edge of the tck in run-test-idle jtag state. the device must already be in programming mode (program_enable instruction). this instruction also forc es the outputs into the outputs_highz. program_security ? this instruction is used to program the electronic security fuse (esf) bit. programming the esf bit protects proprietary designs from being read out. the programming occurs at the second rising edge of the tck in run-test-idle jtag state. the device must already be in programming mode (program_enable instruction). this instruction also forc es the outputs into the outputs_highz. pld_verify ? this instruction is used to read the content of the selected pld and/arch array column. this specific column is preselected by us ing pld_address_shift instruction. this instruction also forces the outputs into the outputs_highz. 0010 0000 0001 0100 0100 / 0000 0100 001 / 1 0000 0000 0001 0100 0100 / 0000 0100 001 / 1 (isppac-powr1220at8-2) (isppac-powr1220at8-1) msb lsb part number (20 bits) 00144h = isppac-powr1220at8-1 20144h = isppac-powr1220at8-2 jedec manufacturer identity code for lattice semiconductor (11 bits) constant 1 (1 bit) per 1149.1-1990
lattice semiconductor isppac-p owr1220at8 data sheet 1-49 discharge ? this instruction is used to discharge the internal programming supply voltage after an erase or pro- gramming cycle and prepares isppac-pow r1220at8 for a read cycle. this instru ction also forces the outputs into the outputs_highz. cfg_address ? this instruction is used to set the address of the cfg array for subsequent program or read operations. this instruction also forces the outputs into the outputs_highz. cfg_data_shift ? this instruction is used to shift data into the cfg register prior to programming or reading. this instruction also forces the outputs into the outputs_highz. cfg_erase ? this instruction will bulk erase the cfg array. th e action occurs at the se cond rising edge of tck in run-test-idle jtag state. the device must already be in programming mode (program_enable instruction). this instruction also forces the outputs into the outputs_highz. cfg_program ? this instruction programs the selected cfg ar ray column. this specific column is preselected by using cfg_address instruction. the programming occurs at the second rising edge of the tck in run-test- idle jtag state. the device must already be in programming mode (program_enable instruction). this instruction also forces the outputs into the outputs_highz. cfg_verify ? this instruction is used to read the content of the selected cfg array co lumn. this specific col- umn is preselected by using cfg_address instruction. this instruction also forc es the outputs into the outputs_highz. bulk_erase ? this instruction will bulk erase all e 2 cmos bits (cfg, pld, ues, and esf) in the isppac- powr1220at8. the device must already be in programming mode (program_enable instruction). this instruction also forces the outputs into the outputs_highz. outputs_highz ? this instruction turns off all of the open-drain output transistors. pins that are programmed as fet drivers will be placed in the active low state. this instruction is effective afte r update-instruction-register jtag state. program_enable ? this instruction enables the programming mode of the isppac-powr1220at8. this instruction also forces the outputs into the outputs_highz. idcode ? this instruction connects the output of the ident ification code data shift (idcode) register to tdo (figure 1-40), to support reading out the identification code. figure 1-40. idcode register program_disable ? this instruction disables the programming mode of the isppac-powr1220at8. the test-logic-reset jtag state can also be used to ca ncel the programming mode of the isppac-powr1220at8. ues_read ? this instruction both reads the e 2 cmos bits into the ues register and places the ues register between the tdi and tdo pins (as shown in figure 1-41), to support programming or reading of the user electronic signature bits. figure 1-41. ues register tdo bit 0 bit 1 bit 2 bit 3 bit 4 bit 27 bit 28 bit 29 bit 30 bit 31 tdo bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15
lattice semiconductor isppac-p owr1220at8 data sheet 1-50 ues_program ? this instruction will program the conten t of the ues register into the ues e 2 cmos memory. the device must already be in programming mode (program_enable instruction). this instruction also forces the outputs into the outputs_highz. erase_done_bit ? this instruction clears the 'done' bit, which prevents the isppac-powr1220at8 sequence from starting. program_done_bit ? this instruction sets the 'done' bit, which enables the isppac-powr1220at8 sequence to start. reset ? this instruction resets the pld sequence and output macrocells. in1_reset_jtag_bit ? this instruction clears the jtag register logic input 'in1.' the pld input has to be con- figured to take input from the jtag register in order for this command to have effect on the sequence. in1_set_jtag_bit ? this instruction sets the jtag register logic input 'in1.' the pld input has to be config- ured to take input from the jtag register in order for this command to have effect on the sequence. pld_verify_incr ? this instruction reads out the pld data register for the current address and increments the address register for the next read. notes: in all of the descriptions above, outputs_highz refers both to the instruction and the state of the digital output pins, in which the open-drains are tri-stated and the fet drivers are pulled low. before any of the above programming instructions are executed, the respective e 2 cmos bits need to be erased using the corresponding erase instruction.
lattice semiconductor isppac-p owr1220at8 data sheet 1-51 package diagrams 100-pin tqfp b lead finish base metal 5. the top of package may be smaller than the bottom 4. dimensions d1 and e1 do not include mold protrusion. datums a, b and d to be determined at datum plane h. allowable mold protrusion is 0.254 mm on d1 and e1 2. all dimensions are in millimeters. 1. dimensioning and tolerancing per ansi y14.5 - 1982. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from the lead tip. 7. a1 is defined as the distance from the seating plane to the lowest point on the package body. exact shape of each corner is optional. 8. dimensions. of the package by 0.15 mm. 6. section b-b: 3. section b-b b 1 c b c 1 0.16 0.13 0.09 c1 0.50 bsc 0.17 0.09 c b1 0.17 b e 0.15 0.20 0.20 0.23 0.22 0.27 14.00 bsc 16.00 bsc 0.45 n l e1 e 100 0.60 0.75 14.00 bsc 16.00 bsc d1 d 0.05 1.35 a2 a1 1.40 - 1.45 0.15 symbol detail 'a' a1 0.10 c min. a-- nom. 1.60 max. 0.20 min. 1.00 ref. 0-7 l b side view seating plane 0.20 c md a-b b top view 8 e d a 3 d gauge plane see detail 'a' c a a2 0.20 4x a-b hd h 0.25 bottom view 3 3 b e1 e d1 0.20 a-bc d 100x notes: pin 1 indicator
lattice semiconductor isppac-p owr1220at8 data sheet 1-52 part number description device number isppac-powr1220at8 - 0xxx100x operating temperature range i = industrial (-40 o c to +85 o c) package t = 100-pin tqfp tn = lead-free 100-pin tqfp* performance grade 01 = 6v to 10v hvout 02 = 6v to 12v hvout device family isppac-powr1220at8 ordering information conventional packaging lead-free packaging part number package pins ISPPAC-POWR1220AT8-01T100I tqfp 100 isppac-powr1220at8-02t100i tqfp 100 part number package pins isppac-powr1220at8-01tn100i lead-free tqfp 100 isppac-powr1220at8-02tn100i lead-free tqfp 100
lattice semiconductor isppac-p owr1220at8 data sheet 1-53 package options 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 6 2 7 2 8 2 9 2 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 0 5 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 0 0 1 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 9 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 8 9 7 8 7 7 7 6 7 in2 in3 out18 out19 out20 s m t i d t a i d t l e s i d t trim6 5 m i r t 4 m i r t 3 m i r t 2 m i r t 1 m i r t 1 n i gndd nc nc nc nc nc nc l c s k l c m gndd vccinp in4 in5 in6 out6 out5_smba out7 out8 vccd out9 out10 out11 out13 out12 out14 out15 out17 out16 gndd j c c v o d t ddn g k c t g o r p c c v cd c v 4 t u o v h 3 gndd nc nc nc nc nc nc t u o v h a d n g s g 1 n o m v 1 n o m v s g 2 n o m v 2 n o m v d e v r e s e r vmon12gs vmon12 trim8 trim7 u o v h t2 u o v h t1 a d n g ddn g vps1 vps0 resetb c d l p lk cdc v a d s vmon11gs vmon11 vmon10gs vmon10 vmon9gs vmon9 vmon8gs vmon8 vmon7gs vmon7 vmon6gs vmon6 vmon5gs vmon5 vmon4gs vmon4 vmon3gs vmon3 reserved vcca isppac-powr1220at8 100-pin tqfp technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: isppacs@la tt icesemi.com internet: www.latticesemi.com
lattice semiconductor isppac-p owr1220at8 data sheet 1-54 revision history date version change summary october 2005 1.0 initial release. march 2006 1.1 pin descriptions table, note 4: clarification for un-used vmon pins to be tied to gndd. correction for i 2 c/adc calculation. may 2006 1.2 updated hvout isource range:12.5a to 100a. adc characteristics table, adc conversion time: added entry for tconvert = 200 s. added footnotes for i 2 c frequency. figure 13, isource 12.5a to 100a. clarified operation of adc conversions. tap instructions, added jtag sample/preload instruction and notes for all jtag instructions october 2006 1.3 data sheet status changed to ?final?. analog specifications table, lowered max. icc to 40 ma. voltage monitors table, tightened input resistor variation to 15%. margin trim dac output characteristics tabl e, increased max. dac output current to +/- 200 a. ac/transient characteristics table, tightene d internal oscillator frequency variation down to 5%. digital specifications table, included v il and v ih specifications for i 2 c interface. august 2007 01.4 changes to hvout pin specifications. june 2008 01.5 added timing diagram and timing parameters to "power-on reset" specifications. modified pld architecture figure to show input registers. updated i 2 c control registers table. vccprog pin usage clarification added. may 2010 01.6 vccprog pin usage further clarified. added product information for isppac-powr1220at8-02. t good changed from a min to a max. isppac-powr1220at8 alternate tdi configuration diagram clarified.

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